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mb9b500b series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf504nb/rb, mb9b f505nb/rb, mb9b f506nb/rb data sheet (full production) publication number mb9b500b - ds706 - 00021 revision 3.0 issue date d ecember 15 , 2014 confidential notice to readers: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document ar e not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. d a t a s h e e t mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential notice on data sheet designations spansion inc. issues data sheets with advance information or preliminary designa tions to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they ha ve the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates tha t spansion inc. is developing one or more specific products, but has not committed any design to production. information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spans ion inc. therefore places the following conditions upon advance information content: this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice. preliminary the preliminary designation indicates that the product development has progressed such tha t a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production i s achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under consideration. spansion places the following conditions upon preliminary content: this document stat es the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the man ufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications. combination some data sheets contain a combination of products with differ ent designations (advance information, preliminary, or full production). this type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the dc charact eristics table and the ac erase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time s uch that no changes or only nominal changes are expected, the preliminary designation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed opt ion, temperature range, package type, or vio range. changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. spansion inc. applies the following conditions to documents in this category: this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. questions regarding these document designations may be directed to your local sales office. mb9b500b series 32 - bit arm ? cortex ? - m3 based microcontroller mb9bf504nb/rb, mb9b f505nb/rb, mb9b f506nb/rb data sheet (full production) publication number mb9b500b - ds706 - 00021 revision 3.0 issue date december 15 , 2014 confidential this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. d eems the products to have been in sufficient production volume such that subsequent versions of this document are not expect ed to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur. ? description the mb9b500b series are a highly integrated 32 - bit microcontroller that target for high - performance and cost - sensitive embedded control applications. the mb9b500b series are based on the arm cortex - m3 processor and on - chip flash memory and sram , and peripheral functions, including motor control timers, adcs and communication interfaces (usb, can, uart, c sio, i 2 c, lin). the products which are described in this data sheet are placed into type 0 product categories in "fm3 f amily peripheral manual". note: arm and cortex are the tradema rks of arm limited in the eu and other countries. d a t a s h e e t 2 mb9b500b-ds706- 00021- 3v0 -e , december 15 , 2014 confidential ? features y 32- bit arm cortex - m3 core ? processor version: r2p0 ? up to 80mhz frequency operation ? memory protection unit (mpu): improve the reliability of an embedded system ? integrated nested vectored interrup t controller (nvic): 1 nmi ( non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management y on - chip memories [flash memory] ? up to 512 k byte ? read cycle: 0wait - cycle@up to 60mhz , 2wait - cycle* above * : instruction pre - fetch buffer is included. s o when cpu access continuously, it becomes 0wait - cycle ? security function for code protection [sram] this series contain a total of up to 64kbyte on-chip sram. this is composed of two independent sram(sram0, sram1). sram0 is connected to i-code bus and ? sram0: up to 32 k byte ? sram1: up to 32 k byte y usb i nterface usb interface is composed of function and host. pll for usb is built - in, usb clock can be generated by multiplication of main clock. [usb function] ? usb2.0 full - s peed supported ? max. 6 endpoi nt supported ? endpoint 0 is control transfer ? endpoint 1 C ? endpoint1 - 5 is comprised double buffer [usb host] ? usb2.0 full /low speed supported ? bulk - transfer and interrupt - transfer and isochronous - transfer s upport ? usb device connected/dis - connected automatically detect ? in/out token handshake packet automatic ally ? max.256 - byte packet - length supported ? wake - up function supported y can interface (max. 2channels) ? compatible with can specification 2.0a/b ? maximum tran sfer rate: 1 mbps ? built - in 32 message buffer d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 3 confidential ? multi - function s erial i nterface (max. 8 channels ) 4 channels with 16 steps 9bit fifo ( ch.4 - ch. 7), 4 channels without fifo ( ch.0 - ch. 3) operation mode is selectable from the followings for each channel . ua rt csio lin i 2 c [uart] full - duplex double buffer selection with or without parity supported built - in dedicated baud rate generator external clock available as a serial clock hardware flow control : automatically control the transmission by cts/rts (only ch .4) various error detect functions available (parity errors, framing errors, and overrun errors) [csio] full - duplex double buffer built - in dedicated baud rate generator overrun error detect function available [lin] lin protocol rev. 2.1 supported full - duple x double buffer master/slave mode supported lin break field generate (can be changed 13 - 16bit length) lin break delimiter generate (can be changed 1 - 4bit length) various error detect functions available (parity errors, framing errors, and overrun errors) [ i 2 c] standard - mode (max.100kbps) / fast - mode (max.400kbps) supported ? external bus interface supports sram, nor & nand flash device up to 8 chip selects 8/16 - bit data width up to 25 - bit address bit maximum area size : up to 256 mbytes ? dma contr oller (8channels) dma controller has an independent bus for cpu, so cpu and dma controller can process simultaneously . 8 independently configured and operated channels transfer can be started by software or request from the built - in peripherals transfer ad dress area: 32bit(4gbyte) transfer mode: block transfer/burst transfer/demand transfer transfer data type: byte/half - word/word transfer block count: 1 to 16 number of transfers: 1 to 65536 d a t a s h e e t 4 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? a/d converter (max. 16channels) [ 12 - bit a/d converter ] successi ve approximation register type built - in 3unit conversion time: 1.0 v # 9 priority conversion available (priority at 2levels) scanning conversion mode built - in fifo f or conversion data storage ( for scan conversion: 16steps, for priority conversion: 4steps) ? base timer (max. 8channels) operation mode is selectable from t he followings for each channel . 16 - bit pwm timer 16 - bit ppg timer 16/32 - bit reload timer 16/32 - bit pwc timer ? multi - func tion t imer (max. 2 unit s ) the multi - function timer is composed of the following blocks. 16 - bit free - run timer 3ch/unit input capture 4ch/unit output compare 6ch/unit a/d activati on compare 3ch/unit waveform generator 3 ch/unit 16 - bit ppg timer 3c h/unit the following function can be used to achieve the motor control. pwm signal output function dc chopper waveform output function dead time function input capture function a/d convertor activate function dtif ( motor emergency stop) interrupt function ? quadrature position /revolution counter (qprc) ( max. 2unit s ) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use up/down counter. the detection edge of the three extern al event input pins ain, bin and zin is configurable. 16 - bit position counter 16 - bit revolution counter two 16 - bit compare registers d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 5 confidential ? dual timer (two 32/16bit down counter) the dual timer consists of two programmable 32/16 - bit down counters. operation mod e is selectable from the followings for each channel . free - running periodic (=reload) one - shot ? watch counter the watch counter is used for wake up from sleep mode. interval timer: up to 64s( m ax . ) @ sub clock : 32.768khz ? watch dog t imer (2channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a " hardware " w atchdog and a " software " watchdog. " hardware " watchdog timer is clocked by the built - in low - speed cr oscillator. therefore hardware" watchdog is active in any low - power consumption mode s except stop mode . ? external interrupt controller unit up to 16 external vectors include one non - maskable interrupt(nmi) ? general purpose i/o port this series can use its pins as general - purpose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in . it can set which i/o port the peripheral function can be allocated. capable of pull - up control per pin capable of reading pin level directly b uilt - in the port relocate function up to 100 high - speed general - purpose i / o ports@1 2 0pin package ? crc (cyclic redundancy check) accelerator the crc accelerator helps a verify data transmission or storage integrity. ccitt crc16 and ieee - 802.3 crc32 are supported. ccitt crc16 generator polynomial: 0x1021 ieee - 802.3 crc32 generator polynomial: 0x04c11db7 d a t a s h e e t 6 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? clock and reset [clo cks] fiv e clock sources (2 ext. osc, 2 c r osc, and main pll) that are dynamically selectable. main clock : 4 mhz to 48mhz sub clock : 32.768 k hz built - in h igh - speed cr clock : 4mhz built - in l ow - speed cr clock : 100khz main pll clock [resets] reset req uests from initx p ins power - on reset software reset w atchdog timers reset l ow - voltage detector reset c lock supervisor reset ? clock super visor (csv) clocks generated by cr oscillators are used to supervise abnormality of the external clo cks. external osc clock failure ( clock stop) is detected, reset is asserted. external osc frequency anomaly is detect ed, interrupt or reset is asserted. ? low voltage detector (lvd) this s eries include 2 - stage monitoring of voltage on the vcc. when the vo ltage falls below the voltage has been set, low voltage detector generates an interrupt or reset. lvd1: error reporting via interrupt lvd2: auto - reset operation ? low - power consumption m ode three low - power consumption modes supported. sleep timer sto p ? debug serial wire jtag debug port (swj - dp) embedded trace macrocells (etm) provide comprehensive debug and trace facilities. ? power supply two power supplies vcc = 2.7v to 5.5v: cor r espond to the wide range voltage . usbvcc = 3.0v to 3.6v : for usb i/o voltage , when usb is used. = 2.7v to 5.5v: when gpio is used . * d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 7 confidential ? product lineup ? memory size product device mb9bf504n b /r b mb9bf505n b /r b mb9bf506n b /r b on - chip flash memory 256kbyte 384kbyte 512kbyte on - chip sram 32kbyte 48kbyte 64kbyte ? function product device mb9bf504n b mb9bf505n b mb9bf506n b mb9bf504r b mb9bf505r b mb9bf506r b pin count 100 120 cpu cortex - m3 freq. 80mhz power supply voltage range 2.7v to 5.5v usb2.0 (function/host) 1ch can interface 2ch(max) dmac 8ch external bus interface addr :25bit (max.) data:8/16 bit cs:5(max.) support : sram , nor flash addr:25bit (max.) data:8/16 bit cs:8(max.) support : sram , nor & nand flash multi - function serial interface (uart/csio/lin/i 2 c) 8ch (max.) base timer (pwc/ reload timer/pwm/ppg) 8ch (max.) mf - timer a/d activation compare 3 ch. 2 units (max.) input capture 4ch . free - run timer 3ch . output compare 6ch . waveform generator 3ch . ppg 3ch . qprc 2ch (max.) dual timer 1 unit watch counter 1 unit crc accelerator yes w atchdog timer 1ch(sw) + 1ch(hw) external interrupts 16pins (max.)+ nmi 1 i/o ports 80pins (max.) 100pins (max.) 12 bit a/d converter 16ch (3 units) csv (clock super visor) yes lvd (low voltage detector) 2ch built - in cr high - speed 4mhz low - speed 100khz debug function swj - dp/etm note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the general i/o port according to your function use. see " ? electrical characteristics 4.ac characteristics (3)built - in cr oscillation characteristics" for accuracy of built - in cr . d a t a s h e e t 8 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? packages product name package mb9bf504n b mb9bf505n b mb9bf506n b mb9bf504r b mb9bf505r b mb9bf506r b lqfp: fpt - 100p - m23 (0.5mm pitc h) ? - lqfp: fpt - 120p - m37 (0.5mm pitch) - ? bga: bga - 112p - m04 (0. 8 mm pitch) ? - ? ? : supported note : refer to " ? package dimensions" for detailed information on each package. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 9 confidential ? pin assignment ? fpt - 100p - m23 (top view) d a t a s h e e t 10 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential ? fpt - 120p - m37 (top view) < note > ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multip le pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin . 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 1 90 2 89 3 88 4 87 5 86 6 85 7 84 8 83 9 82 10 81 11 80 12 79 13 78 14 77 15 76 16 75 17 74 18 73 19 72 20 71 21 70 22 69 23 68 24 67 25 66 26 65 27 64 28 63 29 62 30 61 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 lqfp - 120 vcc p40/tioa0_0/rto10_1/int12_1/mad22 p41/tioa1_0/rto11_1/int13_1/mad21 p42/tioa2_0/rto12_1/mad20 p43/tioa3_0/rto13_1/adtg_7/mad19 p44/tioa4_0/rto14_1/mad18 p45/tioa5_0/rto15_1/mad17 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad16 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad15 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad14 p4b/tiob2_0/ic12_1/zin0_1/mad13 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad12 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad11 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad10 p70/tx0_0/tioa4_2 p71/rx0_0/int13_2/tiob4_2 p72/sin2_0/int14_2 p73/sot2_0/int15_2 p74/sck2_0 md1 md0 x0 x1 vss vss p20/int05_0/crout/ain1_1 p21/sin0_0/int06_1/bin1_1 p22/sot0_0/tiob7_1/zin1_1 p23/sck0_0/tioa7_1/rto00_1 p24/rx1_0/sin2_1/int01_2/rto01_1 p25/tx1_0/sot2_1/rto02_1 p26/sck2_1/rto03_1/mcsx4 p27/int02_2/rto04_1/mcsx5 p28/adtg_4/rto05_1/mcsx6 p1f/an15/adtg_5/frck0_1/mdata15 p1e/an14/rts4_1/dtti0x_1/mdata14 p1d/an13/cts4_1/ic03_1/mdata13 p1c/an12/sck4_1/ic02_1/mdata12 p1b/an11/sot4_1/ic01_1/mdata11 p1a/an10/sin4_1/int05_1/ic00_1/mdata10 p19/an09/sck2_2/mdata9 p18/an08/sot2_2/mdata8 avss avrh avcc p17/an07/sin2_2/int04_1/mwex p16/an06/sck0_1/moex p15/an05/sot0_1/mcsx0 p14/an04/sin0_1/int03_1/mcsx1 p13/an03/sck1_1/mad08 p12/an02/sot1_1/tx1_2/mad09 p11/an01/sin1_1/int02_1/rx1_2 p10/an00 vcc vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/tx0_2/mad00 p63/int03_0/sin5_1/rx0_2/mad01 p64/tioa7_0/sot5_1/int10_2 p65/tiob7_0/sck5_1 p66/sin3_0/adtg_8/int11_2 p67/sot3_0/tioa7_2 p68/sck3_0/tiob7_2/int12_2 p0f/nmix/mad02 p0e/cts4_0/tiob3_2/ic13_0/mad03 p0d/rts4_0/tioa3_2/ic12_0/mad04 p0c/sck4_0/tioa6_1/ic11_0/mad05 p0b/sot4_0/tiob6_1/ic10_0/mad06 p0a/sin4_0/int00_2/frck1_0/mad07 p09/traceclk/tiob0_2/rts4_2 p08/traced3/tioa0_2/cts4_2 p07/traced2/adtg_0/sck4_2 p06/traced1/tiob5_2/sot4_2/int01_1 p05/traced0/tioa5_2/sin4_2/int00_1 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx vcc vcc p50/int00_0/ain0_2/sin3_1/rto10_0/mdata0 p51/int01_0/bin0_2/sot3_1/rto11_0/mdata1 p52/int02_0/zin0_2/sck3_1/rto12_0/mdata2 p53/sin6_0/tioa1_2/int07_2/rto13_0/mdata3 p54/sot6_0/tiob1_2/rto14_0/mdata4 p55/sck6_0/adtg_1/rto15_0/mdata5 p56/sin1_0/int08_2/dtti1x_0/mcsx7 p57/sot1_0/mnale p58/sck1_0/mncle p59/sin7_0/rx1_1/int09_2/mnwex p5a/sot7_0/tx1_1/mnrex p5b/sck7_0 p30/ain0_0/tiob0_1/int03_2/mdata6 p31/bin0_0/tiob1_1/sck6_1/int04_2/mdata7 p32/zin0_0/tiob2_1/sot6_1/int05_2/mdqm0 p33/int04_0/tiob3_1/sin6_1/adtg_6/mdqm1 p34/frck0_0/tiob4_1/tx0_1/mad24 p35/ic03_0/tiob5_1/rx0_1/int08_1/mad23 p36/ic02_0/sin5_2/int09_1/mcsx3 p37/ic01_0/sot5_2/int10_1/mcsx2 p38/ic00_0/sck5_2/int11_1 p39/dtti0x_0/adtg_2 p3a/rto00_0/tioa0_1 p3b/rto01_0/tioa1_1 p3c/rto02_0/tioa2_1 p3d/rto03_0/tioa3_1 p3e/rto04_0/tioa4_1 p3f/rto05_0/tioa5_1 vss d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 11 confidential ? bga - 112p - m04 d a t a s h e e t 12 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential ? list of pin functions ? list of pin numbers t he number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to se lect the pin . pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 1 b1 1 vcc - 2 c1 2 p50 e h int00_0 ain0_2 sin3_1 rto10_0 (ppg10_0) mdata0 3 c2 3 p51 e h int01_0 bin0_2 sot3_1 ( sda3_1) rto11_0 (ppg10_0) mdata1 4 b3 4 p52 e h int02_0 zin0_2 sck3_1 (scl3_1) rto12_0 (ppg12_0) mdata2 5 d1 5 p53 e h sin6_0 tioa1_2 int07_2 rto13_0 (ppg12_0) mdata3 6 d2 6 p54 e i sot6_0 (sda6_0) tiob1_2 rto14_0 (ppg14_0) mdata4 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 13 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 7 d3 7 p55 e i sck6_0 (scl6_0) adtg_1 rto15_0 (ppg14_0) mdata5 8 d5 8 p 56 e h sin1_0 (120pin only) int08_2 dtti1x_0 mcsx7 - - 9 p57 e i sot1_0 (sda1_0) mnale - - 10 p58 e i sck1_0 (scl1_0) mncle - - 11 p59 e h sin7_0 rx1_1 int09_2 mnwex - - 12 p5a e i sot7_0 (sda7_0) tx1_1 mnrex - - 13 p5b e i sck7_0 (scl7_0) 9 e1 14 p30 e h ain0_0 tiob0_1 int03_2 mdata6 d a t a s h e e t 14 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 10 e2 15 p31 e h bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 mdata7 11 e3 16 p32 e h zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 mdqm0 12 e4 17 p33 e h int04_0 tiob3_1 sin6_1 adtg_6 mdqm1 1 3 f1 18 p34 e i frck0_0 tiob4_1 tx0_1 mad24 14 f2 19 p35 e h ic03_0 tiob5_1 rx0_1 int08_1 mad23 15 f3 20 p36 e h ic02_0 sin5_2 int09_1 mcsx3 16 g1 21 p37 e h ic01_0 sot5_2 (sda5_2) int10_1 mcsx2 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 15 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 17 g2 22 p38 e h ic00_0 sck5_2 (scl5_2) int11_1 18 f4 23 p39 e i dtti0x_0 adtg_2 19 g3 24 p3a g i rto00_0 (ppg00_0) tioa0_1 - b2 - vss - 20 h1 25 p3b g i rto01_0 (ppg00_0) tioa1_1 21 h2 26 p3c g i rto02_0 (ppg02_0) tioa2_1 22 g4 27 p3d g i rto03_0 (ppg02_0) tioa3_1 23 h3 28 p3e g i rto04_0 (ppg 04_0) tioa4_1 24 j2 29 p3f g i rto05_0 (ppg04_0) tioa5_1 25 l1 30 vss - 26 j1 31 vcc - 27 j4 32 p40 g h tioa0_0 rto10_1 (ppg10_1) int12_1 mad22 d a t a s h e e t 16 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 b ga - 112 lqfp - 120 28 l5 33 p41 g h tioa1_0 rto11_1 (ppg10_1) int13_1 mad21 29 k5 34 p42 g i tioa2_0 rto12_1 (ppg12_1) mad20 30 j5 35 p43 g i tioa3_0 rto13_1 (ppg12_1) adtg_7 mad19 - k2 - vss - - j3 - vss - - h4 - vss - 31 h5 36 p44 g i tioa4_0 rto14_1 (ppg14_1) mad18 32 l6 37 p45 g i tioa5_0 rto15_1 (ppg14_1) mad17 33 l2 38 c - 34 l4 39 vss - 35 k1 40 vcc - 36 l3 41 p46 d m x0a 37 k3 42 p47 d n x1a 38 k4 43 initx b c 39 k6 44 p48 e h dtti1x_1 int14_1 sin3_2 mad16 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 17 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 40 j6 45 p49 e i tiob0_0 ic10_1 ain0_1 s ot3_2 (sda3_2) mad15 41 l7 46 p4a e i tiob1_0 ic11_1 bin0_1 sck3_2 (scl3_2) mad14 42 k7 47 p4b e i tiob2_0 ic12_1 zin0_1 mad13 43 h6 48 p4c e i tiob3_0 ic13_1 sck7_1 (scl7_1) ain1_2 mad12 44 j7 49 p4d e i tiob4_0 frck1_1 sot7_1 (sda7_1) bin1_2 mad11 45 k8 50 p4e e h tiob5_0 int06_2 sin7_1 zin1_2 mad10 - - 51 p70 e i tx0_0 tioa4_2 d a t a s h e e t 18 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin n o. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 - - 52 p71 e h rx0_0 int13_2 tiob4_2 - - 53 p72 e h sin2_0 int14_2 - - 54 p73 e h sot2_0 (sda2_0) int15_2 - - 55 p74 e i sck2_0 (scl 2_0) 46 k9 56 md1 c d 47 l8 57 md0 c d 48 l9 58 x0 a a 49 l10 59 x1 a b 50 l11 60 vss - 51 k11 61 vcc - 52 j11 62 p10 f k an00 53 j10 63 p11 f l an01 sin1_1 int02_1 rx1_2 - k10 - vss - - j9 - vss - 54 j8 64 p12 f k an02 sot1_1 (sda1_1) tx1_2 mad09 55 h10 65 p13 f k an03 sck1_1 (scl1_1) mad08 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 19 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 56 h9 66 p14 f l an04 sin0_1 int0 3_1 mcsx1 57 h7 67 p15 f k an05 sot0_1 (sda0_1) mcsx0 58 g10 68 p16 f k an06 sck0_1 (scl0_1) moex 59 g9 69 p17 f l an07 sin2_2 int04_1 mwex 60 h11 70 avcc - 61 f11 71 avrh - 62 g11 7 2 avss - 63 g8 73 p18 f k an08 sot2_2 (sda2_2) mdata8 64 f10 74 p19 f k an09 sck2_2 (scl2_2) mdata9 65 f9 75 p1a f l an10 sin4_1 int05_1 ic00_1 mdata10 - h8 - vss - d a t a s h e e t 20 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 66 e11 76 p1b f k an11 sot4_1 (sda4_1) ic01_1 mdata11 67 e10 77 p1c f k an12 sck4_1 (scl4_1) ic02_1 mdata12 68 f8 78 p1d f k an13 cts 4_1 ic03_1 mdata13 69 e9 79 p1e f k an14 rts4_1 dtti0x_1 mdata14 70 d11 80 p1f f k an15 adtg_5 frck0_1 mdata15 - - 8 1 p28 e i adtg_4 rto05_1 (ppg04_1) mcsx6 - - 82 p27 e h int02_2 rto04_1 (ppg04_1) mcsx5 - - 83 p26 e i sck2_1 (scl2_1) rto03_1 (ppg02_1) mcsx4 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 21 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 - - 84 p25 e i tx1_0 sot2_1 (sda2_1) rto02_1 (ppg02_1) - b10 - vss - - c9 - vss - - - 85 p24 e h rx1_0 sin2_1 int01_2 rto01_1 (ppg00_1) 7 1 d10 8 6 p23 e i sck0_0 (scl0_0) tioa7_1 rto00_1 (ppg00_1) 7 2 e8 8 7 p22 e i sot0_0 (sda0_0) tiob7_1 zin1_1 7 3 c11 8 8 p21 e h sin0_0 int06_1 bin1_1 7 4 c10 8 9 p20 e h int05_0 crout ain1_1 75 a11 90 vss - 76 a10 91 vcc - 77 a9 92 p00 e e trstx 78 b9 93 p01 e e tck swclk 79 b11 94 p 02 e e tdi d a t a s h e e t 22 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 80 a8 95 p03 e e tms swdio 81 b8 96 p04 e e tdo swo 82 c8 97 p05 e f traced0 tioa5_2 sin4_2 int00_1 - d8 - vss - 83 d9 98 p06 e f traced1 tiob5_2 sot4_2 (sda4_2) int01_1 84 a7 99 p07 e g traced2 adtg_0 sck4_2 (scl4_2) 85 b7 100 p08 e g traced3 tioa0_2 cts4_2 86 c7 101 p09 e g traceclk tiob0_2 rts4_2 87 d7 102 p0a e h sin4_0 int00_2 frck1_0 mad07 88 a6 103 p0b e i sot4_0 (sda4_0) tiob6_1 ic10_0 mad06 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 23 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 89 b6 104 p0c e i sck4_0 (scl4_0) tioa6_1 ic11_0 mad05 90 c6 105 p0d e i rts4_0 tioa3_2 ic12_0 mad04 91 a5 106 p0e e i cts4_0 tiob3_2 ic13_0 mad03 - d4 - vss - - c3 - vss - 92 b5 107 p0f e j nmix mad02 - - 108 p68 e h sck3_0 (scl3_0) tiob7_2 int12_2 - - 109 p67 e i sot3_0 (sda3_0) tioa7_2 - - 110 p66 e h sin3_0 adtg_8 int11_2 - - 111 p65 e i tiob7_0 sck5_1 (scl5_1) - - 112 p64 e h tioa7_0 sot5_1 (sda5_1) int10_2 d a t a s h e e t 24 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin no. pin name i/o circuit type pin s tate type lqfp - 100 bga - 112 lqfp - 120 93 d6 113 p63 e h int03_0 rx0_2 mad01 - - sin5_1 94 c5 114 p62 e i sck5_0 (scl5_0) adtg_3 tx0_2 mad00 95 b4 115 p61 e i sot5_0 (sda5_0) tiob2_2 uhconx 96 c4 116 p60 e h sin5_0 tioa2_2 int15_1 97 a4 117 usbvcc - 98 a3 118 p80 h o udm0 99 a2 119 p81 h o udp0 100 a1 120 vss - d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 25 confidential ? list of pin functions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 adc adtg_0 a/d converter external trigger input pin . 84 a7 99 adtg_1 7 d3 7 adtg_2 18 f4 23 adtg_3 94 c5 114 a dtg_4 - - 8 1 adtg_5 70 d11 80 adtg_6 12 e4 17 adtg_7 30 j5 35 adtg_8 - - 110 an00 a/d converter analog input pin . anxx describes adc ch.xx. 52 j11 62 an01 53 j10 63 an02 54 j8 64 an03 55 h10 65 an04 56 h9 66 an05 57 h7 67 an 06 58 g10 68 an07 59 g9 69 an08 63 g8 73 an09 64 f10 74 an10 65 f9 75 an11 66 e11 76 an12 67 e10 77 an13 68 f8 78 an14 69 e9 79 an15 70 d11 80 base timer 0 tioa0_0 base timer ch.0 tioa pin . 27 j4 32 tioa0_1 19 g3 24 tioa0_ 2 85 b7 100 tiob0_0 base timer ch.0 tiob pin . 40 j6 45 tiob0_1 9 e1 14 tiob0_2 86 c7 101 base timer 1 tioa1_0 base timer ch.1 tioa pin . 28 l5 33 tioa1_1 20 h1 25 tioa1_2 5 d1 5 tiob1_0 base timer ch.1 tiob pin . 41 l7 46 tiob1_1 10 e2 1 5 tiob1_2 6 d2 6 base timer 2 tioa2_0 base timer ch.2 tioa pin . 29 k5 34 tioa2_1 21 h2 26 tioa2_2 96 c4 116 tiob2_0 base timer ch.2 tiob pin . 42 k7 47 tiob2_1 11 e3 16 tiob2_2 95 b4 115 d a t a s h e e t 26 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 base timer 3 tioa3_0 base timer ch.3 tioa pin . 30 j5 35 tioa3_1 22 g4 27 tioa3_2 90 c6 105 tiob3_0 base timer ch.3 tiob pin . 43 h6 48 tiob3_1 12 e4 17 tiob3_2 91 a5 106 base timer 4 tioa4_0 base timer ch.4 ti oa pin . 31 h5 36 tioa4_1 23 h3 28 tioa4_2 - - 51 tiob4_0 base timer ch.4 tiob pin . 44 j7 49 tiob4_1 13 f1 18 tiob4_2 - - 52 base timer 5 tioa5_0 base timer ch.5 tioa pin . 32 l6 37 tioa5_1 24 j2 29 tioa5_2 82 c8 97 tiob5_0 base timer ch.5 tiob pin . 45 k8 50 tiob5_1 14 f2 19 tiob5_2 83 d9 98 base timer 6 tioa6_1 base timer ch.6 tioa pin . 89 b6 104 tiob6_1 base timer ch.6 tiob pin . 88 a6 103 base timer 7 tioa7_0 base timer ch.7 tioa pin . - - 112 tioa7_1 71 d10 86 tioa7_2 - - 109 tiob7_0 base timer ch.7 tiob pin . - - 111 tiob7_1 72 e8 87 tiob7_2 - - 108 can 0 tx0_0 can interface ch.0 tx output . - - 51 tx0_1 13 f1 18 tx0_2 94 c5 114 rx0_0 can interface ch.0 rx input . - - 52 rx0_1 14 f2 19 rx0_2 93 d6 1 13 can 1 tx1_0 can interface ch.1 tx output . - - 84 tx1_1 - - 12 tx1_2 54 j8 64 rx1_0 can interface ch.1 rx input . - - 85 rx1_1 - - 11 rx1_2 53 j10 63 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 27 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 debug ger swclk serial wire debug interface clock input . 78 b9 93 swdio serial wire debug interface data input / output . 80 a8 95 swo serial wire viewer output . 81 b8 96 tck j - tag test clock input . 78 b9 93 tdi j - tag test data input . 79 b11 94 tdo j - ta g debug data output . 81 b8 96 tms j - tag test mode state input / output . 80 a8 95 traceclk trace clk output of etm . 86 c7 101 traced0 trace data output of etm . 82 c8 97 traced1 83 d9 98 traced2 84 a7 99 traced3 85 b7 100 trstx j - tag test rese t input . 77 a9 92 external bus mad00 e xternal bus interface address bus . 94 c5 114 mad01 93 d6 113 mad02 92 b5 107 mad03 91 a5 106 mad04 90 c6 105 mad05 89 b6 104 mad06 88 a6 103 mad07 87 d7 102 mad08 55 h10 65 mad09 54 j8 64 mad10 45 k8 50 mad11 44 j7 49 mad12 43 h6 48 mad13 42 k7 47 mad14 41 l7 46 mad15 40 j6 45 mad16 39 k6 44 mad17 32 l6 37 mad18 31 h5 36 mad19 30 j5 35 mad20 29 k5 34 mad21 28 l5 33 mad22 27 j4 32 mad23 14 f2 19 mad2 4 13 f1 18 mcsx0 external bus interface chip select output pin . 57 h7 67 mcsx1 56 h9 66 mcsx2 16 g1 21 mcsx3 15 f3 20 mcsx4 - - 83 mcsx5 - - 82 mcsx6 - - 81 mcsx7 8 d5 8 d a t a s h e e t 28 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin no. lqfp - 1 00 bga - 112 lqfp - 120 external bus mdata0 e xternal bus interface data bus . 2 c1 2 mdata1 3 c2 3 mdata2 4 b3 4 mdata3 5 d1 5 mdata4 6 d2 6 mdata5 7 d3 7 mdata6 9 e1 14 mdata7 10 e2 15 mdata8 63 g8 73 mdata9 64 f10 74 mdata10 6 5 f9 75 mdata11 66 e11 76 mdata12 67 e10 77 mdata13 68 f8 78 mdata14 69 e9 79 mdata15 70 d11 80 mdqm0 external bus interface byte mask signal output. 11 e3 16 mdqm1 12 e4 17 mnale external bus interface ale signal to control nand flas h output pin . - - 9 mncle external bus interface cle signal to control nand flash output pin . - - 10 mnrex external bus interface read enable signal to control nand flash . - - 12 mnwex external bus interface write enable signal to control nand flash . - - 11 moex external bus interface read enable signal for sram. 58 g10 68 mwex external bus interface write enable signal for sram. 59 g9 69 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 29 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 external interrupt int00_ 0 external interrupt request 00 input pin . 2 c1 2 int00_1 82 c8 97 int00_2 87 d7 102 int01_0 external interrupt request 01 input pin . 3 c2 3 int01_1 83 d9 98 int01_2 - - 85 int02_0 external interrupt request 02 input pin . 4 b3 4 int02_1 53 j10 63 int02_2 - - 82 int03_0 external interrupt request 03 input pin . 93 d6 113 int03_1 56 h9 66 int03_2 9 e1 14 int04_0 external interrupt request 04 input pin . 12 e4 17 int04_1 59 g9 69 int04_2 10 e2 15 int05_0 external interrupt request 05 input pin . 74 c10 89 int05_1 65 f9 75 int05_2 11 e3 16 int06_1 external interrupt request 06 input pin . 73 c11 88 int06_2 45 k8 50 int07_2 external interrupt request 07 input pin . 5 d1 5 int08_1 external interrupt request 08 inpu t pin . 14 f2 19 int08_2 8 d5 8 int09_1 external interrupt request 09 input pin . 15 f3 20 int09_2 - - 11 int10_1 external interrupt request 10 input pin . 16 g1 21 int10_2 - - 112 int11_1 external interrupt request 11 input pin . 17 g2 22 int 11_2 - - 110 int12_1 external interrupt request 12 input pin . 27 j4 32 int12_2 - - 108 int13_1 external interrupt request 13 input pin . 28 l5 33 int13_2 - - 52 int14_1 external interrupt request 14 input pin . 39 k6 44 int14_2 - - 53 int15 _1 external interrupt request 15 input pin . 96 c4 116 int15_2 - - 54 nmix non - maskable interrupt input . 92 b5 107 d a t a s h e e t 30 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 gpio p00 general - purpose i/o port 0. 77 a9 92 p01 78 b9 93 p02 79 b11 94 p03 80 a8 95 p04 81 b8 96 p05 82 c8 97 p06 83 d9 98 p07 84 a7 99 p08 85 b7 100 p09 86 c7 101 p0a 87 d7 102 p0b 88 a6 103 p0c 89 b6 104 p0d 90 c6 105 p0e 91 a5 106 p0f 92 b5 107 p10 general - purpose i/o port 1. 52 j11 62 p11 53 j10 63 p12 54 j8 64 p13 55 h10 65 p14 56 h9 66 p15 57 h7 67 p16 58 g10 68 p17 59 g9 69 p18 63 g8 73 p19 64 f10 74 p1a 65 f9 75 p1b 66 e11 76 p1c 67 e10 77 p1d 68 f8 78 p1e 69 e 9 79 p1f 70 d11 80 p20 general - purpose i/o port 2. 74 c10 89 p21 73 c11 88 p22 72 e8 87 p23 71 d10 86 p24 - - 85 p25 - - 84 p26 - - 83 p27 - - 82 p28 - - 81 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 31 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 gpio p30 general - purpose i/o port 3. 9 e1 14 p31 10 e2 15 p32 11 e3 16 p33 12 e4 17 p34 13 f1 18 p35 14 f2 19 p36 15 f3 20 p37 16 g1 21 p38 17 g2 22 p39 18 f4 23 p3a 19 g3 24 p3b 20 h1 25 p3c 21 h2 26 p3 d 22 g4 27 p3e 23 h3 28 p3f 24 j2 29 p40 general - purpose i/o port 4. 27 j4 32 p41 28 l5 33 p42 29 k5 34 p43 30 j5 35 p44 31 h5 36 p45 32 l6 37 p46 36 l3 41 p47 37 k3 42 p48 39 k6 44 p49 40 j6 45 p4a 41 l7 46 p4b 42 k7 47 p4c 43 h6 48 p4d 44 j7 49 p4e 45 k8 50 p50 general - purpose i/o port 5. 2 c1 2 p51 3 c2 3 p52 4 b3 4 p53 5 d1 5 p54 6 d2 6 p55 7 d3 7 p56 8 d5 8 p57 - - 9 p58 - - 10 p59 - - 11 p5a - - 12 p5b - - 13 d a t a s h e e t 32 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 gpio p60 general - purpose i/o port 6. 96 c4 116 p61 95 b4 115 p62 94 c5 114 p63 93 d6 113 p64 - - 112 p65 - - 111 p66 - - 110 p67 - - 109 p68 - - 108 p70 general - purpose i/o port 7. - - 51 p71 - - 52 p72 - - 53 p73 - - 54 p74 - - 55 p80 general - purpose i/o port 8. 98 a3 118 p81 99 a2 119 multi function serial 0 sin0_0 multifunction serial interface ch.0 input pin . 73 c11 88 sin0_1 56 h 9 66 sot0_0 (sda0_0) multifunction serial interface ch.0 output pin . this pin operates as so t0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 72 e8 87 sot0_1 (sda0_1) 57 h7 67 s ck0_0 (scl0_0) multifunction serial interface ch.0 clock i/o pin . this pin operates as sck0 when it is used in a uart/csio (operation modes 0 to 2) and as scl0 when it is used in an i 2 c (operation mode 4). 71 d10 86 sck0_1 (scl0_1) 58 g10 68 multi func tion serial 1 sin1_0 multifunction serial interface ch.1 input pin . - - 8 sin1_1 53 j10 63 sot1_0 (sda1_0) multifunction serial interface ch.1 output pin . this pin operates as so t1 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sd a1 when it is used in an i 2 c (operation mode 4). - - 9 sot1_1 (sda1_1) 54 j8 64 sck1_0 (scl1_0) multifunction serial interface ch. 1 clock i/o pin . this pin operates as sck 1 when it is used in a uart/csio (operation modes 0 to 2) and as scl 1 when it is used in an i 2 c (operation mode 4). - - 10 sck1_1 (scl1_1) 55 h10 65 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 33 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 multi function serial 2 sin2_0 multifunction serial interface ch.2 input pin . - - 53 sin2_1 - - 85 sin2_2 59 g9 69 sot2_0 (sda2_0) multifunction serial interface ch.2 output pin . this pin operates as so t2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). - - 54 sot2_1 (sda2_1 ) - - 84 sot2_2 (sda2_2) 63 g8 73 sck2_0 (scl2_0) multifunction serial interface ch.2 clock i/o pin . this pin operates as sck2 when it is used in a uart/csio (operation modes 0 to 2) and as scl2 when it is used in an i 2 c (operation mode 4). - - 55 sck2_1 (scl2_1) - - 83 sck2_2 (scl2_2) 64 f10 74 multi function serial 3 sin3_0 multifunction serial interface ch.3 input pin . - - 110 sin3_1 2 c1 2 sin3_2 39 k6 44 sot3_0 (sda3_0) multifunction serial interface ch.3 output pin . this pin opera tes as so t3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). - - 109 sot3_1 (sda3_1) 3 c2 3 sot3_2 (sda3_2) 40 j6 45 sck3_0 (scl3_0) multifunction serial interface ch.3 clock i/o pin . this pin operates as sck3 when it is used in a uart/csio (operation modes 0 to 2) and as scl3 when it is used in an i 2 c (operation mode 4). - - 108 sck3_1 (scl3_1) 4 b3 4 sck3_2 (scl3_2) 41 l7 46 d a t a s h e e t 34 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin n o. lqfp - 100 bga - 112 lqfp - 120 multi function serial 4 sin4_0 multifunction serial interface ch.4 input pin . 87 d7 102 sin4_1 65 f9 75 sin4_2 82 c8 97 sot4_0 (sda4_0) multifunction serial interface ch.4 output pin . this pin operates as so t4 w hen it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda4 when it is used in an i 2 c (operation mode 4). 88 a6 103 sot4_1 (sda4_1) 66 e11 76 sot4_2 (sda4_2) 83 d9 98 sck4_0 (scl4_0) multifunction serial interface ch.4 clock i/o pin . th is pin operates as sck4 when it is used in a uart/csio (operation modes 0 to 2) and as scl4 when it is used in an i 2 c (operation mode 4). 89 b6 104 sck4_1 (scl4_1) 67 e10 77 sck4_2 (scl4_2) 84 a7 99 rts4_0 multifunction serial interface ch.4 rts ou tput pin . 90 c6 105 rts4_1 69 e9 79 rts4_2 86 c7 101 cts4_0 multifunction serial interface ch.4 cts input pin . 91 a5 106 cts4_1 68 f8 78 cts4_2 85 b7 100 multi function serial 5 sin5_0 multifunction serial interface ch.5 input pin . 96 c4 116 sin5_1 - - 113 sin5_2 15 f3 20 sot5_0 (sda5_0) multifunction serial interface ch.5 output pin . this pin operates as so t5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 95 b4 1 15 sot5_1 (sda5_1) - - 112 sot5_2 (sda5_2) 16 g1 21 sck5_0 (scl5_0) multifunction serial interface ch.5 clock i/o pin . this pin operates as sck5 when it is used in a uart/csio (operation modes 0 to 2) and as scl5 when it is used in an i 2 c (operatio n mode 4). 94 c5 114 sck5_1 (scl5_1) - - 111 sck5_2 (scl5_2) 17 g2 22 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 35 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 multi function serial 6 sin6_0 multifunction serial interface ch.6 input pin . 5 d1 5 sin6_1 12 e4 17 sot6_0 (sda6_0) multifunction serial interface ch.6 output pin . this pin operates as so t6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 6 d2 6 sot6_1 (sda6_1) 11 e3 16 sck6_0 (scl6_0) multifunction serial interface ch.6 clock i/o pin . this pin operates as sck6 when it is used in a uart/csio (operation modes 0 to 2) and as scl6 when it is used in an i 2 c (operation mode 4). 7 d3 7 sck6_1 (scl6_1) 10 e2 15 multi functi on serial 7 sin7_0 multifunction serial interface ch.7 input pin . - - 11 sin7_1 45 k8 50 sot7_0 (sda7_0) multifunction serial interface ch.7 output pin . this pin operates as so t7 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda7 when it is used in an i 2 c (operation mode 4). - - 12 sot7_1 (sda7_1) 44 j7 49 sck7_0 (scl7_0) multifunction serial interface ch.7 clock i/o pin . this pin operates as sck7 when it is used in a uart/csio (operation modes 0 to 2) and as scl7 when it is used in an i 2 c (operation mode 4). - - 13 sck7_1 (scl7_1) 43 h6 48 d a t a s h e e t 36 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 multi function timer 0 dtti0x_0 input signal controlling wave form generator outputs rto00 to rto05 o f multi - function timer 0 . 18 f4 23 dtti0x_1 69 e9 79 frck0_0 16 - bit free - run timer ch.0 external clock input pin . 13 f1 18 frck0_1 70 d11 80 ic00_0 16 - bit input capture ch.0 input pin of multi - function timer 0 . icxx desicribes chanel number. 17 g 2 22 ic00_1 65 f9 75 ic01_0 16 g1 21 ic01_1 66 e11 76 ic02_0 15 f3 20 ic02_1 67 e10 77 ic03_0 14 f2 19 ic03_1 68 f8 78 rto00_0 (ppg00_0) wave form generator output of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg 0 output modes . 19 g3 24 rto00_1 (ppg00_1) 71 d10 86 rto01_0 (ppg00_0) wave form generator output of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg 0 output modes . 20 h1 25 rto01_1 (ppg00_1) - - 85 rto02_0 (ppg0 2_0) wave form generator output of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg 0 output modes . 21 h2 26 rto02_1 (ppg02_1) - - 84 rto03_0 (ppg02_0) wave form generator output of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg 0 output modes . 22 g4 27 rto03_1 (ppg02_1) - - 83 rto04_0 (ppg04_0) wave form generator output of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg 0 output modes . 23 h3 28 rto04_1 (ppg04_1) - - 82 rto05_0 (ppg04_0) wave form generator output of multi - function timer 0. this pin operates as ppg04 when it is used in ppg 0 output modes . 24 j2 29 rto05_1 (ppg04_1) - - 81 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 37 confidential module pin name function pin no. lqfp - 100 bga - 112 l qfp - 120 multi function timer 1 dtti1x_0 input signal controlling wave form generator outputs rto 10 to rto 15 of multi - function timer 1 . 8 d5 8 dtti1x_1 39 k6 44 frck1_0 16 - bit free - run timer ch.1 external clock input pin . 87 d7 102 frck1_1 44 j7 4 9 ic10_0 16 - bit input capture ch.0 input pin of multi - function timer 1 . icxx desicribes chanel number. 88 a6 103 ic10_1 40 j6 45 ic11_0 89 b6 104 ic11_1 41 l7 46 ic12_0 90 c6 105 ic12_1 42 k7 47 ic13_0 91 a5 106 ic13_1 43 h6 48 rto 10_0 (ppg10_0) wave form generator o utput of multi - function timer 1 . this pin operates as ppg10 when it is used in ppg 1 output modes . 2 c1 2 rto10_1 (ppg10_1) 27 j4 32 rto11_0 (ppg10_0) wave form generator o utput of multi - function timer 1 . this pin o perates as ppg10 when it is used in ppg 1 output modes . 3 c2 3 rto11_1 (ppg10_1) 28 l5 33 rto12_0 (ppg12_0) wave form generator o utput of multi - function timer 1 . this pin operates as ppg12 when it is used in ppg 1 output modes . 4 b3 4 rto12_1 (ppg12 _1) 29 k5 34 rto13_0 (ppg12_0) wave form generator o utput of multi - function timer 1 . this pin operates as ppg12 when it is used in ppg 1 output modes . 5 d1 5 rto13_1 (ppg12_1) 30 j5 35 rto14_0 (ppg14_0) wave form generator o utput of multi - function timer 1 . this pin operates as ppg14 when it is used in ppg 1 output modes . 6 d2 6 rto14_1 (ppg14_1) 31 h5 36 rto15_0 (ppg14_0) wave form generator output of multi - function timer 1 . this pin operates as ppg14 when it is used in ppg 1 output modes . 7 d3 7 rto15_1 (ppg14_1) 32 l6 37 d a t a s h e e t 38 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 quadrature position/ revolution counter 0 ain0_0 q prc ch.0 ain input pin . 9 e1 14 ain0_1 40 j6 45 ain0_2 2 c1 2 bin0_0 q prc ch.0 bin input pin . 10 e2 15 bin0_1 41 l7 46 bin0_2 3 c2 3 zin0_0 q prc ch.0 zin input pin . 11 e3 16 zin0_1 42 k7 47 zin0_2 4 b3 4 quadrature position/ revolution counter 1 ain1_1 q prc ch.1 ain input pin . 74 c10 89 ain1_2 43 h6 48 bin1_1 q pr c ch.1 bin input pin . 73 c11 88 bin1_2 44 j7 49 zin1_1 q prc ch.1 zin input pin . 72 e8 87 zin1_2 45 k8 50 usb udm0 usb function / host d C d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 39 confidential module pin name function pin no. lqfp - 100 bga - 112 lqfp - 120 reset initx external reset input . a reset is valid when initx=l. 38 k4 43 mode md0 mode 0 pin. during normal operation, md0=l must be input. during serial programming to flash memory, md0=h must be input. 47 l8 57 md1 mode 1 pin. input must always be at the "l" level. 46 k 9 56 power vcc power pin . 1 b1 1 vcc 26 j1 31 vcc 35 k1 40 vcc 51 k11 61 vcc 76 a10 91 usbvcc 3.3v power supply port for usb i/o . 97 a4 117 gnd vss gnd pin . - b2 - vss 25 l1 30 vss - k2 - vss - j3 - vss - h4 - vss 34 l4 39 vss 50 l11 60 vss - k10 - vss - j9 - vss - h8 - vss - b10 - vss - c9 - vss 75 a11 90 vss - d8 - vss - d4 - vss - c3 - vss 100 a1 120 clock x0 main clock (oscillation) input pin . 48 l9 58 x0a sub clock (oscillation) in put pin . 36 l3 41 x1 main clock (oscillation) i/o pin . 49 l10 59 x1a sub clock (oscillation) i/o pin . 37 k3 42 crout built - in high - speed cr - osc clock output port . 74 c10 89 analog power avcc a/d converter analog power pin . 60 h11 70 av rh a/d converter analog reference voltage input pin . 61 f11 71 analog gnd avss a/d converter gnd pin . 62 g11 72 c - pin c power stabilization capacity pin . 33 l2 38 d a t a s h e e t 40 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? i/o circuit type type circuit remarks a ? oscillation feedback resistor : approximately 1m ? with standby mode control b ? cmos level hysteresis input ? pull - up resistor : approximately 50k c ? cmos level hysteresis input pull - up resistor digital input clock input x0 x1 standby mode control mode input d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 41 confiden tial type circuit remarks d ? it is possible to se lect the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 20m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol =4ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control d a t a s h e e t 42 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol =4ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol =4ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input is available digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pul l - up resistor control digital input standby mode c ontrol analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 43 confiden tial type circuit remarks g ? cmos level output ? cmos le vel hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h ? it is possible to select the usb io / gpio function. when the usb io is selected. ? full - speed, low - speed control when the gpio is selected. ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 25.3 ma, i ol = 19.7 ma digital output digital output pull - up resistor control digital input standby mode c ontrol gpio digital output gpio digital input/output direction gpio digital input gpio digital input circuit control udp output udp input differential input usb/gpio select udm input udm output usb digital input/output direction gpio digital out put gpio digital input/output direction gpio digital input gpio digital input circuit control p-ch p-ch n-ch r udp0/p81 udm0/p80 di f ferential d a t a s h e e t 44 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes prec autions that must be observed to minimize the chance of failure and to obtain higher reliability from your spansion semiconductor devices. 1. precautions for product design this section describes precautions when designing electronic equipment using semicondu ctor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? re commended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within t he recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. user s considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power s upply and input/output functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to perma nent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large curren t flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of op eration. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high volta ges, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of lat ch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute ma ximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. code: ds00 - 00004 - 3 e d a t a s h e e t december 15 , 2014 , mb9b 500b - ds706 - 00021 - 3v0 - e 45 confidential ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor dev ices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related to usage of devices spansion semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and m easurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or w here extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before s uch use. the company will not be responsible for damages arising from such use without prior approval. 2. precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during so ldering, you should only mount under spansion 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liqu id solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to spansion recommended mounting conditions. if socket mounti ng is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be verified before m ounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased sus ceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. spansion recommends the solder reflow method, and has established a ranking of mounting conditions for each product. u sers are advised to mount packages in accordance with spansion ranking of recommended conditions. ? lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be redu ced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a p ackage that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. d a t a s h e e t 46 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential st ore products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, spansion packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the spansion recommended conditions for baking. condition: 125 c /24 h ? static electr icity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on th e level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other hi ghly static - prone materials for storage of completed board assemblies. d a t a s h e e t december 15 , 2014 , mb9b 500b - ds706 - 00021 - 3v0 - e 47 confidential 3. precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to ch emical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments invol ving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of spansion products in other special environmental conditions should consult with sales representatives. please check the latest handling precautions at the following url. htt p:// www.spansion .com/ fjdocuments/ fj/ datasheet/e - ds/ds00 - 00004 .pdf d a t a s h e e t 48 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? handling devices ? power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions su ch as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a bypass capacitor between each power supply pin and gnd pin , between avcc pin and avss pin near this device. ? stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended opera ting conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc val ue in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. ? crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the devi ce to malfunction. design the printed circuit board so tha t x0 / x1, x0a/ x1a pins , the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. ? using an external clock when using an exter nal clock, the clock signal should be input to the x0 ,x0a pin only and the x1 ,x1a pin should be kept open. ? handling when using multi function serial pin as i 2 c pin if it is using multi function serial pin as i 2 c pin s , p - ch tran sistor of digital output is always disable. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to external i 2 c bus system with power off. ? example of using an external clock device x0 (x0a) x1 (x1a) open d a t a s h e e t december 15 , 2014 , mb9b 500b - ds706 - 00021 - 3v0 - e 49 confidential ? c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of cap acitance variation due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothin g capacitor of about 4.7f would be recommended for this series. ? mode pins (md0, md 1) connect the md pin (md0, md1) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and v cc pins or v ss pins is as short as possible and the connectio n impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. ? notes on power - on turn power on/off in the following order or at the same time . if not using the a/d converter, connect avcc =vcc and avss = vss. t urning on : v cc ? usbvcc vcc ? av cc ? avrh t urning off : usb v cc ? vcc avrh ? av cc ? vcc ? serial communication there is a possibility to receive wrong d ata due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , restransmit the data. ? differences in features among the products with different memory sizes and between flash products and mask products the electric characteristics including power consumption, esd, latch - up, noise charact eristics, and oscillation characteristics among the products with different memory sizes and between flash products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. device c vss c s gnd d a t a s h e e t 50 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential ? block diagram ? memory size see " ? memory size " in " ? product lineup " to confirm the memory size. a h b - a p b b r i d g e : a p b 2 ( m a x . 4 0 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x . 4 0 m h z ) a h b - a h b b r i d g e a h b - a p b b r i d g e : a p b 0 ( m a x . 4 0 m h z ) m u l t i - l a y e r a h b ( m a x . 8 0 m h z ) f l a s h i / f c o r t e x - m 3 c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . o n - c h i p f l a s h 2 5 6 / 3 8 4 / 5 1 2 k b y t e m u l t i f u n c t i o n t i m e r x 2 m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 7 ) * h w f l o w c o n t r o l ( c h . 4 ) 1 6 - b i t f r e e r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 3 c h . 1 6 - b i t p p g 3 c h . w a t c h c o u n t e r u n i t 0 g p i o u s b 2 . 0 ( h o s t / f u n c ) p h y c s v l v d e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i p o w e r o n r e s e t t p i u r o m t a b l e e t m s r a m 0 1 6 / 2 4 / 3 2 k b y t e s w j - d p s r a m 1 1 6 / 2 4 / 3 2 k b y t e i d s y s m b 9 b f 5 0 4 b / 5 0 5 b / 5 0 6 b b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . m p u n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r u n i t 1 u n i t 2 t r s t x , t c k t d i , t m s t r a c e d [ 3 : 0 ] , t r a c e c l k x 0 a v c c , a v s s , a v r h a n [ 1 5 : 0 ] t i o a [ 7 : 0 ] t i o b [ 7 : 0 ] i c 0 [ 3 : 0 ] d t t i [ 1 : 0 ] x r t o 0 [ 5 : 0 ] f r c k [ 1 : 0 ] u d p 0 , u d m 0 c t d o x 1 x 0 a x 1 a s c k [ 7 : 0 ] s i n [ 7 : 0 ] s o t [ 7 : 0 ] i n t [ 1 5 : 0 ] n m i x p 0 [ f : 0 ] , p 1 [ f : 0 ] , ? ? p x [ x : 0 ] , i n i t x u s b v c c m o d e - c t r l i r q - m o n i t o r p i n - f u n c t i o n - c t r l m d [ 1 : 0 ] r e g u l a t o r q p r c 2 c h . a i n [ 1 : 0 ] b i n [ 1 : 0 ] z i n [ 1 : 0 ] l v d c t r l c a n c a n c r c a c c e l e r a t o r t x 0 , r x 0 t x 1 , r x 1 i c 1 [ 3 : 0 ] u s b c l o c k c t r l c a n p r e s c a l e r p l l a d t g [ 8 : 0 ] r t s 4 c t s 4 e x t e r n a l b u s i f m a d [ 2 4 : 0 ] m d a t a [ 1 5 : 0 ] m c s x [ 7 : 0 ] , m o e x , m w e x , m n a l e , m n c l e m n w e x , m n r e x , m d q m [ 1 : 0 ] u h c o n x r t o 1 [ 5 : 0 ] p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 51 confidential ? m emory map ? memory map (1) f l a s h 0 x 0 0 0 0 _ 0 0 0 0 0 x 0 0 1 0 _ 0 0 0 0 0 x 2 0 0 0 _ 0 0 0 0 0 x 1 f f 8 _ 0 0 0 0 s r a m 0 s r a m 1 0 x 2 0 0 8 _ 0 0 0 0 r e s e r v e d 0 x 2 2 0 0 _ 0 0 0 0 r e s e r v e d 3 2 m b y t e b i t b a n d a l i a s 0 x 2 4 0 0 _ 0 0 0 0 r e s e r v e d 0 x 4 0 0 0 _ 0 0 0 0 p e r i p h e r a l s 0 x 4 2 0 0 _ 0 0 0 0 0 x 6 0 0 0 _ 0 0 0 0 0 x e 0 0 0 _ 0 0 0 0 c o r t e x - m 3 p r i v a t e p e r i p h e r a l s 0 x e 0 1 0 _ 0 0 0 0 r e s e r v e d 0 x f f f f _ f f f f 3 2 m b y t e b i t b a n d a l i a s r e s e r v e d 0 x 4 4 0 0 _ 0 0 0 0 0 x 4 0 0 0 _ 0 0 0 0 0 x 4 1 f f _ f f f f f l a s h i / f 0 x 4 0 0 0 _ 1 0 0 0 r e s e r v e d 0 x 4 0 0 1 _ 0 0 0 0 c l o c k / r e s e t 0 x 4 0 0 1 _ 2 0 0 0 0 x 4 0 0 1 _ 1 0 0 0 s w w d t h w w d t 0 x 4 0 0 1 _ 5 0 0 0 r e s e r v e d 0 x 4 0 0 1 _ 3 0 0 0 d u a l t i m e r 0 x 4 0 0 1 _ 6 0 0 0 r e s e r v e d 0 x 4 0 0 2 _ 0 0 0 0 p e r i p h e r a l s a r e a m f t u n i t 0 0 x 4 0 0 2 _ 1 0 0 0 m f t u n i t 1 0 x 4 0 0 2 _ 2 0 0 0 r e s e r v e d p p g 0 x 4 0 0 2 _ 4 0 0 0 0 x 4 0 0 2 _ 5 0 0 0 b a s e t i m e r 0 x 4 0 0 2 _ 6 0 0 0 q p r c 0 x 4 0 0 2 _ 7 0 0 0 a / d c 0 x 4 0 0 2 _ 8 0 0 0 r e s e r v e d 0 x 4 0 0 3 _ 0 0 0 0 e x t i 0 x 4 0 0 3 _ 1 0 0 0 i n t - r e q . r e a d 0 x 4 0 0 3 _ 2 0 0 0 0 x 4 0 0 3 _ 3 0 0 0 0 x 4 0 0 3 _ 4 0 0 0 0 x 4 0 0 3 _ 5 0 0 0 0 x 4 0 0 3 _ 6 0 0 0 0 x 4 0 0 3 _ 7 0 0 0 r e s e r v e d g p i o l v d u s b c l o c k c t r l c a n p r e s c a l e r 0 x 4 0 0 3 _ 8 0 0 0 m f s 0 x 4 0 0 3 _ 9 0 0 0 c r c 0 x 4 0 0 3 _ a 0 0 0 w a t c h c o u n t e r 0 x 4 0 0 3 _ b 0 0 0 r e s e r v e d 0 x 4 0 0 4 _ 0 0 0 0 e x t - b u s i / f u s b c h . 0 0 x 4 0 0 5 _ 0 0 0 0 0 x 4 0 0 6 _ 0 0 0 0 c a n c h . 0 0 x 4 0 0 6 _ 1 0 0 0 c a n c h . 1 0 x 4 0 0 6 _ 2 0 0 0 d m a c 0 x 4 0 0 6 _ 3 0 0 0 r e s e r v e d 0 x 4 0 0 3 _ f 0 0 0 r e s e r v e d r e s e r v e d 0 x 4 0 0 2 _ e 0 0 0 c r t r i m 0 x 4 0 0 2 _ f 0 0 0 r e s e r v e d 0 x 4 0 0 6 _ 4 0 0 0 r e s e r v e d s e c u r i t y / c r t r i m 0 x 0 0 1 0 _ 2 0 0 0 p l e a s e r e f e r t o t h e n e x t p a g e f o r t h e m e m o r y s i z e d e t a i l s . e x t e r n a l d e v i c e a r e a 0 x 7 0 0 0 _ 0 0 0 0 r e s e r v e d d a t a s h e e t 52 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential ? memory map (2) *: see " mb9b500/400/300/100/mb9a100 series flash programming m anual " for sector s tructure of flash. s a 1 0 - 1 1 ( 6 4 k b x 2 ) s a 8 - 9 ( 4 8 k b x 2 ) s a 4 - 7 ( 8 k b x 4 ) s a 1 0 - 1 3 ( 6 4 k b x 4 ) s a 8 - 9 ( 4 8 k b x 2 ) s a 4 - 7 ( 8 k b x 4 ) s a 1 0 - 1 5 ( 6 4 k b x 6 ) s a 8 - 9 ( 4 8 k b x 2 ) s a 4 - 7 ( 8 k b x 4 ) 0 x 0 0 0 0 _ 0 0 0 0 0 x 2 0 0 0 _ 0 0 0 0 0 x 1 f f f _ 8 0 0 0 s r a m 0 3 2 k b y t e s r a m 1 3 2 k b y t e 0 x 2 0 0 8 _ 0 0 0 0 r e s e r v e d s e c u r i t y 0 x 0 0 1 0 _ 0 0 0 0 0 x 0 0 0 8 _ 0 0 0 0 r e s e r v e d 0 x 2 0 0 0 _ 8 0 0 0 c r t r i m m i n g 0 x 0 0 1 0 _ 1 0 0 0 0 x 0 0 1 0 _ 2 0 0 0 r e s e r v e d s r a m 1 1 6 k b y t e s r a m 0 1 6 k b y t e 0 x 0 0 0 0 _ 0 0 0 0 0 x 0 0 0 0 _ 0 0 0 0 0 x 1 f f f _ a 0 0 0 r e s e r v e d s e c u r i t y 0 x 0 0 1 0 _ 0 0 0 0 0 x 0 0 0 6 _ 0 0 0 0 c r t r i m m i n g 0 x 0 0 1 0 _ 1 0 0 0 0 x 0 0 1 0 _ 2 0 0 0 r e s e r v e d 0 x 1 f f f _ c 0 0 0 r e s e r v e d s e c u r i t y 0 x 0 0 1 0 _ 0 0 0 0 0 x 0 0 0 4 _ 0 0 0 0 c r t r i m m i n g r e s e r v e d 0 x 2 0 0 8 _ 0 0 0 0 r e s e r v e d 0 x 2 0 0 0 _ 4 0 0 0 0 x 2 0 0 0 _ 0 0 0 0 0 x 0 0 1 0 _ 1 0 0 0 0 x 0 0 1 0 _ 2 0 0 0 s r a m 1 2 4 k b y t e s r a m 0 2 4 k b y t e 0 x 2 0 0 0 _ 6 0 0 0 0 x 2 0 0 0 _ 0 0 0 0 0 x 2 0 0 8 _ 0 0 0 0 r e s e r v e d m b 9 b f 5 0 6 n b / r b m b 9 b f 5 0 5 n b / r b m b 9 b f 5 0 4 n b / r b f l a s h 5 1 2 k b y t e f l a s h 3 8 4 k b y t e f l a s h 2 5 6 k b y t e d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 53 confidential ? peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserve d 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserv ed 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_1fff multi - function timer unit 1 0x4002_2000 0x4002_3fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature posi tion/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff inter nal cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt controller 0x4003_1000 0x 4003_1fff interrupt request batch - read function 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5fff low voltage detector 0x4003_6000 0x4003_6fff usb clock generator 0x4003_7000 0x4003_7fff can prescaler 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_efff reserved 0x4003_f000 0x4003_ffff external memory interface 0x4004_0000 0 x4004_ffff ahb usb ch . 0 0x4005_0000 0x4005_ffff reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_1000 0x4006_1fff reserved 0x4006_2000 0x4006_2fff can ch . 0 0x4006_3000 0x4006_3fff can ch . 1 0x4006_4000 0x41ff_ffff reserved d a t a s h e e t 54 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential ? pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the " l " level. ? initx=1 this is the period when the initx pin is the " h " level. ? spl=0 this is the status that standby pi n level setting bit (spl) in standby mode control register (stb_ctl) is set to " 0 " . ? spl=1 this is the status that standby pin level setting bit (spl) in standby mode control register (stb_ctl) is set to " 1 " . ? input enabled indicates that the input function can be used. ? internal input fixed at " 0 " this is the status that the input function cannot be used. internal input is fixed at " l " . ? hi - z indicates that the output drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled . ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a po rt, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indic ates that the trace function can be used . d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 55 confidential ? list of pin status pin status type function group power - on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 a ma in crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled b main crystal oscillator output pin h output/ i nternal input fixed at " 0 " / o r i nput enabled h output / i nternal input fixed at " 0 " h output / i nternal input fixed at " 0 " maintain previous state / h output at oscillation stop (*1) / i nternal input fixed at " 0 " maintain previous state/ h output at oscillation stop (*1)/ i nternal input fixed at " 0 " maintain previous state/ h output at oscillation s top (*1)/ i nternal input fixed at " 0 " c initx input pin pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled pull - up / i nput enabled d mode input pin input enabled input enabled input enabled i nput enabled input enabled input enabled e jtag select ed hi - z pull - up / i nput enabled pull - up / i nput enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / i nternal input fixed at " 0 " f trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output external interrupt enabled selected maintain previous state gpio selected , or othe r than above resource selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " d a t a s h e e t 56 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin status type function group power - on reset or low voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 g trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected , or other than above resource selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " h external interrupt enabled selected setting disabled se tting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected , or other than above resource selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " i gpio selected , resource selected hi - z hi - z / i nput enabled hi - z / i nput enabled maintain previous state maintain previous state hi - z / i nternal input fixed at " 0 " j nmix selected setting disabled setting disabled setting disabled maintain previous state maintain p revious state maintain previous state gpio selected , or other than above resource selected hi - z hi - z / i nput enabled hi - z / i nput enabled hi - z / i nternal input fixed at " 0 " d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 57 confidential pin status type function group power - on reset or low voltage detection state i nitx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 k ana log input selected hi - z hi - z / i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i n ternal input fixed at " 0 " / a nalog input enabled gpio selected , or other than above resource selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / i nternal input fixed at " 0 " l external interrup t enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state analog input selected hi - z hi - z / i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled hi - z/ i nternal input fixed at " 0 " / a nalog input enabled gpio selected , or other than above resource selected settin g disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / i nternal input fixed at " 0 " m gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled d a t a s h e e t 58 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential pin status type function group power - on reset or low voltage detection state initx input state device int ernal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 n gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator output pin hi - z / internal input fixed at " 0 " hi - z / internal input fixed at " 0 " hi - z / internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop (*2)/ internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop (*2)/ internal input fixed at " 0 " o gpio selected hi - z hi - z/ input enabled hi - z/ input ena bled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " usb i/o pin setting disabled setting disabled setting disabled maintain previous state hi - z at transmission/ input enabled/ internal input fixed at " 0 " a t reception hi - z at transmission/ input enabled/ internal input fixed at " 0 " at reception *1 : oscillation is stopped at sub timer mode , low speed cr timer mode, and stop mode. *2 : oscillation is stopped at stop mode. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 59 confidential ? electrical characteristics 1. ab solute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1, * 2 vcc vss - 0.5 vss + 6.5 v power supply voltage (for usb) * 1, * 3 usbvcc vss - 0.5 vss + 6.5 v analog power supply voltage * 1, * 4 avcc vss - 0.5 vss + 6.5 v analog reference voltage * 1, * 4 avrh vss - 0.5 vss + 6.5 v input voltage * 1 v i vss - 0.5 vcc + 0.5 ( 1 v ia vss - 0.5 avcc + 0.5 ( 1 v o vss - 0.5 vcc + 0.5 ( clamp - 2 +2 ma * 8 clamp total maximum current clamp ] +20 ma * 8 " l " level maximum output current* 5 i ol - 10 ma 4ma type 20 ma 12ma type 39 ma p80, p81 " l " level average output curre nt* 6 i olav - 4 ma 4ma type 12 ma 12ma type 19.7 ma p80, p81 " l " level total maximum output current ol - 100 ma " l " level total average output current* 7 olav - 50 ma " h " level maximum output current* 5 i oh - - 10 ma 4ma type - 20 ma 12ma type - 39 ma p80, p81 " h " level average output current* 6 i ohav - - 4 ma 4ma type - 12 ma 12ma type - 25.3 ma p80, p81 " h " level total maximum output current oh - - 100 ma " h " level total average output current* 7 ohav - - 50 ma power consumption p d - 800 mw storage temperature t stg - 55 + 150 ? d a t a s h e e t 60 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential * 8 : ? see " ? list of pin functions " and " ? i/o circuit type " about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input . ? the +b signal should always be applied a limiting resistance placed between the +b signal a nd the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive curre nt is low, such as in the low - power consumpsion modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device po wer supply is off (not fixed at 0v), the power supply is provided from the pins, so that incomplete operation may result. ? the following is a r ecommended circuit example ( i/o equivalent circuit ) . < w arning > semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. r protection diode p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output +b input (0v to 16v) d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 61 confidential 2. recommended operating conditions ( vss = avss = 0.0v ) parameter sym bol conditions value unit remarks min max power supply voltage vcc - 2.7 * 4 5.5 v power supply voltage for usb usbvcc - 3.0 3.6 ( s - 1 10 f 3 operating temperature fpt - 120p - m21 fpt - 120p - m37 fpt - 100p - m20 fpt - 100p - m23 bga - 112p - m04 ta when mounted on four - layer pcb - 40 + 85 ? ? ? ? c pin" in " ? handling devices" for the connect ion of the smoothing capacitor. * 4 : in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is u sed) or built - in low - speed cr is possible to operate only. < warning > the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when t he device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with re spect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. d a t a s h e e t 62 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential 3. dc characteristics (1) current rating (vcc = avcc = usbvcc = 2.7v to 5.5v, vss = avss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks typ* 3 max* 4 run mode current icc v cc pll run mode cpu : 80mhz, peripheral : 40mhz, flash 2wait frwtr.rwt = 10 fsyndn.sd = 000 96 118 ma *1 , *5 cpu : 60mhz, peripheral : 30mhz, flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 76 94 ma *1 , *5 cpu : 80mhz, peripheral : 40mhz, flash 5wait frwtr.rwt = 10 fsyndn.sd = 011 66 82 ma *1 , *5 cpu : 60mhz, peripheral : 30mhz, flash 3wait frwtr.rwt = 00 fsyndn.sd = 011 52 65 ma *1 , *5 h igh - speed cr run mode cpu/peripheral : 4mhz* 2 flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 6.0 9.2 ma * 1 s ub run mode cpu/peripheral : 32khz flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 0.2 2.24 ma *1 , *6 l ow - speed cr run mode cpu/peripheral : 100khz flash 0wait frwtr.rwt = 00 fsyndn.sd = 000 0.3 2.36 ma *1 sleep mode current iccs pl l sleep mode peripheral : 40mhz 43 54 ma *1 , *5 h igh - speed cr sleep mode peripheral : 4mhz* 2 3.5 6.2 ma *1 s ub sleep mode peripheral : 32khz 0.15 2.18 ma *1 , *6 l ow - speed cr sleep mode peripheral : 100khz 0.22 2.27 ma *1 *1:when a l l ports are fixed. *2: when setting it to 4mhz by trimming. * 3 : ta=+25c, v cc =3.3v * 4 : ta=+ 8 5c, v cc =5.5v *5: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 6 : when using the crystal oscillator of 32 khz(inclu ding the current consumption of the oscillation circuit ) d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 63 confidential (vcc = avcc = usbvcc = 2.7v to 5.5v, vss = avss = 0v, ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks typ * 2 max * 3 t imer mode current i cct v cc main timer mode ta = + 25 ? ? ? ? cch stop mode ta = + 25 ? ? cc =3.3v * 3 : v cc =5.5v *4: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit ) * 5 : when using the crystal oscillator of 3 2 khz(including the current consumption of the oscillation circuit ) low - v oltage d etection current (v cc = 2.7v to 5.5v, v ss = 0v, ta = - 40c to + 8 5c) parameter symbol pin name conditions value unit remarks typ max low - voltage detection circu it (lvd) power supply current i cclvd vcc at operation for interrupt 2 10 flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, ta = - 40c to + 8 5c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc at write/erase 13 24 ma a/d converte r current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, ta = - 40c to + 8 5c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 2.3 3.6 ma at stop 0.1 2 ccavrh avrh at 1unit operation avrh=5.5v 2.2 3.0 ma at stop 0.03 0.6 d a t a s h e e t 64 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential (2) pin characteristics (v cc = av cc = 2.7v to 5.5v, vss = avss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks mi n typ max " h " level input voltage (hysteresis input) v ih s cmos hysteresis input pin, md0,1 - v cc 0.8 - v cc + 0.3 v " l " level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0,1 - vss - 0.3 - v cc 0.2 v "h" level output voltage v oh 4ma type v cc oh = - 4 ma vcc - 0.5 - vcc v v cc < 4.5 v i oh = - 2 ma 12ma type v cc oh = - 12 ma vcc - 0.5 - vcc v v cc ? oh = - 8 ma p80, p81 v cc ? oh = - 25.3 ma vcc - 0.4 - vcc v v cc < 4.5 v i oh = - 13.4 ma "l" level output voltage v ol 4ma type v cc ? o l = 4 ma vss - 0.4 v v cc < 4.5 v i o l = 2 ma 12ma type v cc ? o l = 12 ma vss - 0.4 v v cc ? o l = 8 ma p80, p81 v cc ? o l = 19.7 ma vss - 0.4 v v cc < 4.5 v i o l = 11.9 ma input leak current i il - - - 5 - 5 pu pull - up pin v cc ? ? in other than v cc , v ss , av cc , av ss , avrh - - 5 15 pf d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 65 confidential 4. ac characteristics (1) main clock input characteristics ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 x1 vcc ? ? ? ? cylh v cc ? ? wh /t cylh p wl /t cylh 45 55 % when using external clock input clock rise time and fall time t cf t cr - - 5 ns when using external clock internal operating clock * 1 frequency f cm - - - 80 mhz master clock f cc - - - 80 mhz base clock (hclk/fclk) f cp0 - - - 40 mhz apb0 bus clock * 2 f cp1 - - - 40 mh z apb1 bus clock * 2 f cp 2 - - - 40 mhz apb2 bus clock * 2 internal operating clock * 1 cycle time t cycc - - 12.5 - ns base clock (hclk/fclk) t cycp0 - - 25 - ns apb0 bus clock * 2 t cycp1 - - 25 - ns apb1 bus clock * 2 t cyc p2 - - 25 - ns apb2 bus clock * 2 *1: for more information about each internal operating clock , see " c hapter 2 - 1 : clock " in " fm3 family peripheral manual ". *2: for about each apb bus which each peripheral is connected to , see " ? block diagram" in this data sheet. d a t a s h e e t 66 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential (2) sub clock input characteristics ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min typ max input frequency f cl x0a x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 wh /t cyll p wl /t cyll 45 - 55 % when using external clock (3) built - in cr oscillation characteristics built - in hi gh - speed cr ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol conditions va lue unit remarks min typ max clock frequency f crh ta = + 25 ? 1 ta = 0 ? ? ? ? ? ? cr wt - - - 50 2 *1: in the case of using the values in cr trimming area of flash memory at shipment for frequency trimming. *2: f requency stable time is time to stable of the frequency of the high - speed cr . clock after the trim value is set. after setti ng the trim value, the period when the frequency stability time passes can use the high - speed cr clock as a source clock. built - in low - speed cr (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 67 confidential (4 - 1 ) operating conditions of main and usb pll (in the case of using main clock for input of pll) ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time (lock up time)* 1 t lock 100 - - plli 4 - 30 mh z pll multiple rate - 4 - 30 multiple pll macro oscillation cloc k frequency f pllo 60 - 120 mh z main pll clock frequency* 2 f clkpll - - 80 mh z usb clock frequency* 3 f clkspll - - 48 mh z after the m frequency division *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more informatio n about main pll clock (clkpll), see "c hapter 2 - 1 : clock" in "fm3 family peripheral manual". *3: for more information about usb clock, see "c hapter 2 - 2 : usb clock generation" in "fm3 family peripheral manual communication macro part". (4 - 2) operating conditions of main pll(in the case of using built - in high speed cr) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol value unit remarks min typ ma x pll oscillation stabilization wait time (lock up time)* 1 t lock 100 - - plli 3.8 4 4.2 mh z pll multiple rate - 15 - 28 multiple pll macro oscillation clock frequency f pllo 57 - 120 mh z main pll clock frequency* 2 f c lkpll - - 80 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see "c hapter 2 - 1 : clock" in "fm3 family peripheral manual". note: make sure to input to the main pll source clock, the high - speed cr clock (clkhc) that the frequency has been trimmed. main clock (clkmo) k divider pll input clock usb pll m divi der usb clock n divider usb pll connection pll macro oscillation clock k di vider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection high - speed cr clock (clkhc) main clock (clkmo) d a t a s h e e t 68 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential (5) reset input characteristics ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns (6) power - on reset timing ( v cc = 2.7 v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name value unit remarks min max power supply rising time tr vcc 0 - ms power supply shut down time toff 1 - ms time until releasing power - on reset tprt 0.422 0.704 ms glossary ? vcc_minimum : minimum v cc of recommended operating conditions ? vd h _minimum : minimum release voltage of low - v oltage detection reset . see " 7 . low - v oltage detection characteristics " 0 . 2 v v d h _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e t r 0 . 2 v 0 . 2 v t o f f d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 69 confidential (7) external bus timing asynchronous sram mode ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max m oex min pulse width t oew moex vcc hclk 1 - 3 - ns vcc ? ? ? oel - av moex mad24 to 00 vcc ? ? ? oeh - ax moex mad24 to 00 vcc ? ? ? ? oel - csl moex mcsx vcc ? ? ? ? oeh - c sh moex mcsx vcc ? ? ? ds - oe moex mdata15 to 0 vcc ? ? ? dh - oe moex mdata15 to 0 vcc ? ? ? ? csl - wel mcsx mw ex vcc hclk 1 - 5 - ns vcc ? hclk 1 - 10 - mwex ? ? ? weh - csh mcsx mwex vcc hclk 1 - 5 - ns vcc ? hclk 1 - 10 - address ? ? av - wel mwex mad24 to 00 vcc hclk 1 - 5 - n s vcc ? hclk 1 - 1 5 - mwex ? ? weh - ax mwex mad24 to 00 vcc hclk 1 - 5 - ns vcc ? hclk 1 - 1 5 - mwex ? ? ? wel - dqml mwex mdqm0 to 1 vcc ? ? ? ? weh - dqmh mwex mdqm0 to 1 vcc ? wew mwex vcc hclk 1 - 3 - ns vcc ? ? ? wel - dv mwex mdata15 to 0 vcc ? ? ? weh - dx mwex mdata15 to 0 vcc hclk 1 - 5 - ns vcc ? hclk 1 - 15 - note: w hen the external load capacitance = 50pf. d a t a s h e e t 70 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential v il v ih v oh mcsx0 to 7 mad24 to 00 moex mdata15 to 0 t oew v ol v ol v oh t oel - av v ol v oh t oel - csl v ol v oh v ih v il t ds - oe t dh - oe t oeh - ax read sram read hclk t cyc v oh v oh t oeh - csh mwex mdata15 to 0 v oh v ol v ol v oh write mcsx0 to 7 mad24 to 00 v ol v ol v oh v ol v oh sram write hclk t cyc v oh mdqm0 to 1 v oh t wel - dqml v ol v ol v oh t weh - dx t weh - ax t csl - wel t wew t weh - csh t weh - dqmh t wel - dv t av - wel d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 71 confidential nand flash mode ( v cc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max m nrex min pulse width t nrew mnrex v cc hclk 1 - 3 - ns vcc ? ? ? ds - nre mnrex mdata 15 to 0 vcc ? ? ? dh - nre mnrex mdata15 to 0 vcc ? ? ? aleh - nwel mnale mnwex vcc hclk 1 - 5 - ns vcc ? hclk 1 - 1 5 - mnwex ? ? nweh - alel mnale mnwex vcc hclk 1 - 5 - ns vcc ? hclk 1 - 1 5 - mncle ? ? cleh - nwel mncle mnwex vcc hclk 1 - 5 - ns vcc ? hclk 1 - 1 5 - mnwex ? ? nweh - clel mncle mnwex vcc hclk 1 - 5 - ns vcc ? hclk 1 - 1 5 - mnwex min pulse width t nwew mnwex vcc hclk 1 - 3 - ns vcc ? ? ? nwel - dv mnwex mdata15 to 0 vcc ? ? ? nweh - dx mnwex mdata15 to 0 vcc hclk 1 - 5 - ns vcc ? hclk 1 - 1 5 - note: when the external load capacitance = 50pf. d a t a s h e e t 72 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential v il v ih mnrex mdata15 to 0 v ol v oh v ih v il t ds - nre t dh - nre read nand flash read t nrew hclk t cyc v oh v oh mdata15 to 0 v oh v ol v ol v oh write nand flash write hclk t cyc mnwex v oh v ol t nwew v ol v oh t nweh - dx v oh v ol mncle mnale t aleh - nwel t nwel - dv t nweh - alel t cleh - nwel t nweh - clel d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 73 confidential (8) base timer input timing timer input timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tioan/tiobn (when using as eck,tin ) - 2 t cycp - ns trigger input tim ing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl tioan/tiobn (when using as tgin ) - 2 t cycp - ns note: t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is connected to, see " ? block diagram" in this data sheet. t tiwh v ihs v ihs v ils v ils t tiw l v ihs v ils tgin t trgh v ihs v ils t trgl d a t a s h e e t 74 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential (9) csio / uart timing csio (spi = 0, scinv = 0 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions v cc ? 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sck x master mode 4tcycp - 4tcycp - ns sck ? ? slovi sckx sotx - 30 +30 - 20 + 20 ns sin ? ? ivshi sckx sinx 50 - 30 - ns sck ? ? shixi sckx sinx 0 - 0 - ns serial clock " l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock " h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? slove sckx sotx - 50 - 30 ns sin ? ? ivshe sckx sinx 10 - 10 - ns sck ? ? shixe sckx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes: the above characteris tics apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? block diagram " in this data sheet. these characteristics only gu a rantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not g ua ranteed. w hen the external load capacitance = 50pf. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 75 confidential master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe d a t a s h e e t 76 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential csio ( spi = 0, scinv = 1 ) ? (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions vcc ? 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck ? ? shovi sckx sotx - 30 +30 - 20 + 20 ns sin ? ? ivsli sckx sinx 50 - 30 - ns sck ? ? slixi sckx sinx 0 - 0 - ns serial clock " l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock " h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? shove sckx sotx - 50 - 30 ns sin ? ? ivsle sckx sinx 10 - 10 - ns sck ? ? slixe sckx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes: the above characteristic s apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time. about the apb bus number which mu lti - function serial is connected to , see " ? block diagram " in this data sheet. these characteristics only gu a rantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not gu a ranteed. w hen the external load capacita nce = 50pf. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 77 confidential master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe d a t a s h e e t 78 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential csio ( spi = 1, scinv = 0 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions vcc ? 4.5v vcc 4 .5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck ? ? shovi sckx sotx - 30 +30 - 20 + 20 ns sin ? ? ivsli sckx sinx 50 - 30 - ns sck ? ? slixi sckx sinx 0 - 0 - ns sot ? ? sovli sckx sotx 2tcycp - 30 - 2tcycp - 30 - ns serial clock " l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock " h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? shove sckx s ot x - 50 - 30 ns sin ? ? ivsle sckx sinx 10 - 10 - ns sck ? ? slixe sc kx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes: the above characteristics apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? block diagram " in this data sheet. these characteristics only gu a rantees the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not gu a ranteed. w hen the external load capacitance = 50pf. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 79 confidential master mode slave mode *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe d a t a s h e e t 80 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential csio ( spi = 1, scinv = 1 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions vcc ? 4.5v vcc 4.5v unit min max min max serial clock cycle time t scyc sckx master mode 4tcycp - 4tcycp - ns sck ? ? slovi sckx sotx - 30 +30 - 20 + 20 ns sin ? ? ivshi sckx sinx 50 - 30 - ns sck ? ?? shixi sckx sinx 0 - 0 - ns sot ? ? sovhi sckx sotx 2tcycp - 30 - 2tcycp - 30 - ns serial clock " l" pulse width t slsh sckx slave mode 2tcycp - 10 - 2tcycp - 10 - ns serial clock " h" pulse width t shsl sckx tcycp + 10 - tcycp + 10 - ns sck ? ? slove sckx s ot x - 50 - 30 ns sin ? ? ivshe sckx sinx 10 - 10 - ns sck ? ? shixe sc kx sinx 20 - 20 - ns sck fall time tf sckx - 5 - 5 ns sck rise time tr sckx - 5 - 5 ns notes: the above characteristics apply to clk synchronous mode. t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to , see " ? block diagram " in this data sheet. these characteristics only gu a rantee the same relocate port number. for example, the combination of sc kx_0 and sotx_1 is not gu a ranteed. w hen the external load capacitance = 50pf. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 81 confidential master mode slave mode uart e xternal clock input ( ext = 1 ) (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol conditions min max unit remarks serial clock " l" pulse width t slsh c l = 50pf tcycp + 10 - ns serial clock " h" pulse width t shsl tcycp + 10 - ns sck fall time tf - 5 ns sck rise time tr - 5 ns t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh sck sot sin sck sot sin s ck t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t s h s l t r t s l s h t s l o v e v i l v i l v i l v i h v i h v i h v o h v o l v o h v o l v i h v i l v i h v i l t i v s h e t s h i x e t f d a t a s h e e t 82 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential (10) external input timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditio ns value unit remarks min max input pulse width t inh t inl adtg - 2 t cycp * - ns a/d converter trigger input frck x free - run timer input clock icxx input capture dttixx - 2 t cycp * - ns w ave form generator int xx , nmix except timer mode , stop mode 2 t cycp + 100 * - ns external interrupt nmi timer mode , stop mode 500 - ns * : t cycp indicates the apb bu s clock cycle time . about the apb bus number which the a/d converte r, multi - function timer , external interrupt are connected to , see " ? block diagram" in this data sheet. t inh v ils v ihs v ihs v ils t inl d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 83 confidential (11) quadrature position/revolution counter timing (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2 t cycp * - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - bin rise time from ain pin "h" level t aubu pc_mode2 or pc_ m ode3 ain fall time from bin pin "h" level t buad pc_mode2 or pc_mode3 bin fall time from ain pin "l" level t adbd pc_mode2 or pc_mode3 ain rise time from bin pin "l" level t bdau pc_mode2 or pc_mode3 ain rise time from bin pin "h" level t buau pc_mode2 or pc_mode3 bin fall time from ain pin "h" level t aubd pc_mode2 or pc_mode3 ain fall time from bin pin "l" leve l t bdad pc_mode2 or pc_mode3 bin rise time from ain pin "l" level t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc="0" zin pin "l" width t zll qcr:cgsc="0" ain/bin rise and fall time from determined zin level t zabe qcr:cgsc="1" determine d zin level from ain/bin rise and fall time t abez qcr:cgsc="1" *: t cycp indicates the apb bus clock cycle time. about the apb bus number which the quadrature position/revolution counter is connected to , see " ? block diagram " in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll d a t a s h e e t 84 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 85 confidential (12 ) i2c timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol conditio ns standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 50pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda ? ? ? hdsta 4.0 - 0.6 - low 4.7 - 1.3 - high 4.0 - 0.6 - ? ? ? susta 4.7 - 0.6 - ? ? ? ? hddat 0 3.45 * 2 0 0.9 * 3 ? ? ? ? sudat 250 - 100 - ns stop condition setup time scl ? ? ? susto 4.0 - 0.6 - buf 4.7 - 1.3 - sp - 2 t cycp * 4 - 2 t cycp * 4 - ns *1 : r and c represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2 : the maximum t hddat must satisfy that it doesn't extend at least "l" period (t low ) of device's scl signal. *3 : fast - mode i 2 c bus device can be used on s tandard - mode i 2 c bus syste m as long as the device satisfies the requirement of "t sudat 250 ns". *4 : t cycp is the apb bus clock cycle time. about the apb bus number that i2c is connected to, see " ? block diagram" in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more. to use fast - mode, set the apb bus clock at 8 mhz or more. sda s cl d a t a s h e e t 86 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential (13 ) etm timing ( vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name con ditio ns val u e unit remarks min max data hold t etmh traceclk traced3 - 0 vcc ? trace traceclk vcc trace vcc hclk traceclk traced[3:0] d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 87 confidential (14 ) jtag timing (vcc = 2.7v to 5.5v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditi ons value unit remarks min max tms,tdi setup time t jtags tck tms,tdi vcc ? jtagh tck tms,tdi vcc ? jtagd tck tdo vcc ? tck tms/ tdi tdo d a t a s h e e t 88 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential 5. 12bit a/d converter electrical charac teristics for the a/d converter . (vcc = avcc = 2.7v to 5.5v, vss = avss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 2 4.5 lsb avrh = 2.7v to 5.5v differential nonlinearity - - - 2 2.5 lsb zero transition voltage v zt an xx - 5 20 mv full - scale transition voltage v fst an xx - avrh 10 avrh 20 mv conversion time - - 1.0* 1 - - 1 - - avcc < 4.5v sampling time ts - *2 - - ns avcc 4 avcc < 4. 5v state transition time to operation permission tstt - - - 2.5 ain - - - 14.5 pf analog input resistance r ain - - - 0.93 k - - - - 4 lsb analog po rt input current - an xx - - 5 - an xx av ss - avrh v reference voltage - avrh 2.7 - av cc v *1: the conversion time is the value of sampling time(ts) + compare time(tc). the condition of the minimum conv ersion time is the following. avcc 4.5v , hclk=72mhz sampling time: 0.222 s compare time: 0. 778 s avcc < 4.5v, hclk=54mhz sampling time: 0.333 s compare time: 2.333 s ensure that it satisfies the value of the sampling time (ts) and compare clock cycle (tcck). for setting of the sampling time and compare clock cycle, see " c hapter 1 - 1 : a/d converter " in " fm3 family peripheral manual analog macro part ". the register s setting of the a/d conv erter are reflected in the operation according to the apb bus clock timing. the sampling clock and compare clock is generated from the base clock (hclk). about the apb bus number which the a/d converter is connected to, see " ? block diagram" in this data sh eet. *2: a necessary sampling time changes by external impedance. ensure that it s et the sampling time to satisfy ( equation 1 ) *3: the compare time ( tc ) is the value of ( equation 2) *4: when 12bit a/d conve rter is used at avcc<4.5v, there is a limitation as follows. please set the hclk frequency under 54mhz. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 89 confidential (equation 1) ts ( r ain + rext ) c ain 9 ts : sampling time r ain : input resistance of a/d = 0.93 k 4.5 av cc 5.5 input resistance of a/d = 2.04 k 2.7 av cc < 4 .5 c ain : input capacity of a/d = 1 4.5 pf 2.7 av cc 5.5 rext : output impedance of external circuit ( equatio n 2 ) tc = tcck 14 tc : compare time tcck : comrare clock cycle rext r ain c ain analog signal source an xx analog input pin c omparator d a t a s h e e t 90 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? definition of 1 2 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonl inearity : deviation of the line between the zero - transition poi nt (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to ch ange the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst C z t 4094 n : a/d converter digital output value. v z t : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 91 confidential 6. usb characteristics ( vcc = 2.7v to 5.5v, usbvcc = 3.0v to 3.6v, vss = 0v , ta = - 40 ? c to + 85 ? c ) parameter symbol pin name conditions value unit remarks min max input charact - eristics input high level voltage v ih udp 0 , udm 0 - 2.0 usbv cc + 0.3 v *1 input low level voltage v il - vss - 0.3 0.8 v *1 differential input sensitivity v di - 0.2 - v *2 different common mode input voltage v cm - 0.8 2.5 v *2 output charact - erstics output high level voltage v oh external pull - down resistance = 15 k ol external pu ll - up resistance = 1.5 k crs - 1.3 2.0 v *4 r ise time t fr full speed 4 20 ns *5 f all time t ff full speed 4 20 n s *5 rise / fall time matching t frfm full speed 90 111.11 % *5 output impedance z drv full speed 28 44 lr low speed 75 300 ns *7 fall time t lf low speed 75 300 n s *7 rise/ fall time matching t lrfm low speed 80 125 % *7 *1 : the switching threshold voltage of single - end - receiver of usb i/o buffer is set as within v il (max) = 0.8 v , v ih (min) = 2.0 v (ttl input standard). there are some hysteres e s to lower noise sensitivity. *2 : u se differential - receiver to receive usb differential data signal. differential - receiver has 200 mv of differential input sensitivity when the differentia l data input is within 0.8 v to 2.5 v to the local ground reference level. above voltage range is the common mode input voltage range. 0.2 0.8 1.0 2.5 c ommon mode input voltage [v] minimum differential input sensitivity [v] d a t a s h e e t 92 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential *3 : the output drive capability of the driver is below 0.3 v at low - state (v ol ) (to 3.6 v and 1.5 k load), and 2.8 v or above (to the vss and 1.5 k load) at high - state (v oh ). *4 : the cross voltage of the external differential output signal (d + /d ? ) o f usb i/o buffer is within 1.3 v to 2.0 v . *5 : they ind icate rise time (trise) and fall time (tfall) of the full - speed differential data signal. they are defined by the time between 10 % and 90 % of the output signal voltage. for full - speed buffer, tr/tf ratio is regulated as within ? 10 % to minimize rfi emissio n. trise 10% 90% tfall rising time falling time d - d+ 10% 90% d - d+ min 1. 3v max 2. 0v v crs specifie d range full - speed buffer rs = 27 l = 50pf c l = 50pf. rs = 27 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 93 confidential *6 : usb full - speed connection is performed via twist pair cab l e shield with 90 15% characteristic impedance ( differential mode ) . usb standard defines that output impedance of usb driver must be in range from 28 to 44 . so, discrete series resistor (rs) addition is defined in order to satisfy the above definition and keep balance. when using this usb i/o , use it with 25 to 30 ( recommendation value 27 ) series resistor rs. *7 : they indicate rise time (trise) and fall time (tfall) of the low - speed differential data signal. they are defined by the time between 10 % and 90 % of the output signal voltage. see ? low - speed load (compliance load) for conditions of external load. trise 10% 90% tfall rising time falling time d - d+ 10% 90% full - speed buffer rs rs txd+ txd - 3 - state enable 28 d a t a s h e e t 94 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? low - speed load (upstream port load) - reference 1 ? low - speed load (downstream port load) - reference 2 ? low - speed load (compliance load) rpu= 1.5 k l =200 to 600 pf c l =200 to 600pf low - speed buffer rs = 2 7 l = 50 to 150pf c l =50 to 150pf rs = 27 l = 200 to 450pf c l =200 to 450pf rs = 27 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 95 confidential 7. low - v oltage d etection c haracteristics (1) low - v oltage d etection r eset ( ta = - 40 ? c to + 85 ? c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2. 2 0 2.4 0 2.60 v when voltage drops released voltage vdh - 2.3 0 2.50 2.70 v when voltage rises (2) interrupt of l ow - v oltage d etection ( ta = - 40 ? c to + 85 ? c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0000 2.58 2.8 3.02 v when voltage drops released voltage vdh 2.67 2.9 3.13 v when voltage rises detected voltag e vdl svhi = 0001 2.76 3.0 3.24 v when voltage drops released voltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 0010 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.04 3.3 3.56 v when voltage rises detected voltage vdl svhi = 0011 3.31 3.6 3.88 v when voltage drops released voltage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl svhi = 0100 3.40 3.7 3.99 v when voltage drops released voltage vdh 3.50 3.8 4.10 v when voltage rises detected voltage vd l svhi = 0111 3.68 4.0 4.32 v when voltage drops released voltage vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svhi = 1000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 1001 3.86 4.2 4.53 v when voltage drops released voltage vdh 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 2040 tcycp * cycp indicates the apb2 bus clock cycle time. d a t a s h e e t 96 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential 8. flash memory write/erase characteristi cs (1) write / erase time ( vcc = 2.7v to 5.5v , ta = - 40 ? c to + 85 ? c ) parameter value unit remarks typ * max * sector erase time large sector 1.6 7.5 s in cludes write time prior to internal erase small sector 0.4 2.1 half w ord (16 bit) write time 25 400 (2) erase/write cycles and data hold time erase/write cycles (cycle) d ata hold time (year ) remarks 1,000 20 * 10,000 10 * 100,000 5 * * : a t a verage + 85 ? c d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 97 confidential 9. return time from low - power consumption mode (1 ) return f actor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving t he return factor to starting the program operation. ? return c ount t ime ( v cc = 2.7v to 5.5v , ta = - 40 c to + 8 5 c ) parameter symbol value unit remarks typ max* sleep mode ticnt t cycc ns high - speed cr timer mode, main timer mode, pll timer mode 33 1 00 ? operation example of return from l ow - p ower consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t 98 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in ret urn factor by the kind of low - power consumption mode. notes: ? the return factor is different in each l ow - p ower consumption modes. see "c hapter 6 : low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual about the return factor from l ow - p ower consumption mode. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6 : low power consumption mode" in "fm3 family periphera l manual". i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 99 confidential (2) return f actor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. ? return c ount t ime ( v cc = 2.7v to 5.5v , ta = - 40 c to + 8 5 c ) parameter symbol va lue unit remarks typ max* sleep mode trcnt 82 181 ? operation example of return from l ow - p ower consumption mode (by initx) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e d a t a s h e e t 100 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see "c hapter 6 : low power consumption mode" and "operations of stand by modes" in fm3 family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6 : low power consumption mode" in "fm3 family peripheral man ual". ? the time during the power - on reset/low - voltage detection reset is excluded. see "(6) power - on reset timing in 4. ac characteristics in ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the main pll clock stabilization wait time. ? the internal res ource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 000 21 - 3v0 - e 101 confidential ? example of characteristic power supply current (pll run mode, pll sleep mode ) power supply current ( sub run mode ) power supply current ( sub sleep mode ) icc normal operation(pll) temperature characteristics vcc:5.5v, cpu:80mh, peripheral:40mh,flash 2wait 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[ ] power supply current [ma] iccs sleep operation(pll) temperature characteristics vcc:5.5v, peripheral:40mh 0 10 20 30 40 50 60 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[ ] power supply current [ma] icc normal operation(sub oscillation) temperature characteristics vcc:5.5v, cpu/peripheral:32khz 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] icc normal operation(sub oscillation) temperature characteristics(semi-log) vcc:5.5v, cpu/peripheral:32khz 1 10 100 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] (log) iccs sleep operation(sub oscillation) temperature characteristics vcc:5.5v, peripheral:32khz 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] iccs sleep operation(sub oscillation) temperature characteristics(semi-log) vcc:5.5v, peripheral:32khz 1 10 100 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] (log) d a t a s h e e t 102 mb9b500b - ds706 - 00021 - 3v0 - e, dcember 15 , 2014 confidential power supply current ( sub timer mode ) power supply current ( stop mode ) i cct timer mode(sub oscillation) temperature characteristics vcc:5.5v, lvd is off 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] i cct timer mode(sub oscillation) temperature characteristics(semi-log) vcc:5.5v, lvd is off 1 10 100 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] (log) i cch stop mode (sub oscillation) temperature characteristics vcc:5.5v, lvd is off 0 50 100 150 200 250 300 350 400 450 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] i cch stop mode (sub oscillation) temperature characteristics(semi-log) vcc:5.5v, lvd is off 1 10 100 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 temperature ta[] power supply current [ a] (log) d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 103 confidential ? ordering information part number on - chip flash memory on - chip sram package packing mb9bf504nbpmc - g - jne2 256kbyte 32kbyte plastic ? lqfp (0.5mm pitch),100 - pin ( fpt - 1 0 0p - m23) tray mb9bf505nbpmc - g - jne2 384kbyte 48kbyte mb9bf506nbpmc - g - jne2 512kbyte 64kbyte mb9bf504rbpmc - g - jne2 256kbyte 32kbyte plastic ? lqfp (0.5mm pitch),120 - pin ( fpt - 120p - m37) mb9bf505rbpmc - g - jne2 384kbyte 48kbyte MB9BF506RBpmc - g - jne2 512kbyte 64kbyte mb9bf504nbbgl - g - y e1 256kbyte 32kbyte plastic ? pfbga (0.8mm pitch),112 - pin (bga - 112p - m04) mb9bf505nbbgl - g - ye1 384kbyte 48kbyte mb9bf506nbbgl - g - ye1 512kbyte 64kbyte d a t a s h e e t 104 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential ? package dimensions 100-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 14.00 mm 14.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.65 g 100-pin plastic lqfp (fpt-100p-m23) (fpt-100p-m23) c 2009-2010 fujitsu semiconductor limited f100034s-c-3-4 16.000.20(.630.008)sq 1 25 51 76 75 100 0.50(.020) 0.220.05 m 0.08(.003) *14.000.10(.551.004)sq 26 50 0.1450.055 (.006.002) 0.08(.003) "a" index 0 ~8 0.500.20 0.100.10 (stand off) + .008 + 0.20 (mounting height) - 0.10 1.50 .059 - .004 ( ) 0.600.15 0.25(.010) dimensions in mm (inches). note:the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. details of "a" part (.004.004) (.009.002) (.020.008) (.024.006) d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 105 confidential 120-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 16.0 mm 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.88 g code (reference ) p-lfqfp120-16 16-0.50 120-pin plastic lqfp (fpt -120p-m37) (fpt-120p-m37) c 2010 fujitsu semiconductor limited f120037sc(1)-1-1 16.00 0.10(.630 .004) sq 18.00 0.20(.709 .008) sq 1 30 31 61 91 60 90 120 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) ( ) 0.08(.003) "a" index .059 C .004 +.008 C 0.10 +0.20 1.50 (mounting height) 0? ~8 ? (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.05 (.004 .002) details of "a" part (stand off) * lead no. C 0.03 +0.05 0.145 C .001 +.002 .006 dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. d a t a s h e e t 106 mb9b500b - ds706 - 00021 - 3v0 - e , december 15 , 2014 confidential 112-ball plastic pfbga ball pitch 0.80 mm pa ck age width pa ck age length 10.00 10.00 mm lead shape soldering ball sealing method plastic mold ball si ze 0.45 mm mounting height 1.45 mm max. we ight 0.22 g 112-ball plastic pfbg a (bga-112p-m04 ) (bga-112p-m04) c 2003-2010 fujitsu semiconductor limited b112004s-c-2-3 10.000.10(.394.004) (.049.008) 1.250.20 (seated height) 6 f index (index area) 10.000.10 (.394.004) (112-0.18.004) 112-0.45010 0.350.10 (.014.004) (stand off) 0.10(.004) s b a g h j k le dc ba 7 8 9 10 11 5 4 3 2 1 0.80(.031) ref ref 0.80(.031) 0.08(.003) b a s m 0.20(.008) sb s a s 0.20(.008) dimensions in mm (inches). note: the values in parentheses are reference values. d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 107 confidential ? major changes page section change results revision 1.0 - - initial release revision 2.0 - - corrected series name and part number: mb 9b500 a series mb 9b500 b series, mb9bf504n a mb9bf504nb , mb9bf504 r a mb9bf504 r b , mb9b f505 n a mb9b f505 nb , mb9b f505r a mb9b f505r b , mb9b f506 n a mb9b f506 nb , mb9b f506r a mb9b f506r b revision 2.1 - - company name and layout design change revision 3.0 2 ? features ? usb interface added the description of pll for usb 3 ? features ? external bus interface added the descript ion of maximum area size 8 ? packages deleted the description of es 17 ? list of pin functions list of pin numbers modified the pin state type of p4e from i to h 32 - 35 ? list of pin functions list of pin functions added lin to the description of sotxx 42 ? i/o circuit type added the description of i 2 c to the type of e and f 42, 43 ? i/o circuit type added about +b input 48 ? handling devices added " ? s tabilizing power supply voltage" 48 ? handling devices ? c rystal oscillator circuit added the following d escription " evaluate oscillation of your using crystal oscillator by your mount board." 49 ? handling devices ? c pin changed the description 5 0 ? block diagram modified the block diagram 5 0 ? memory size changed to the following description see " ? memory si ze" in " ? product lineup" to confirm the memory size. 5 1 ? m emory map memory map (1) modified the area of "extarnal device area" 5 2 ? memory map memory map(2) added the summary of flash memory sector and the note 59, 60 ? electrical characteristics 1. ab solute maximum ratings added the clamp maximum current added the output current of p80 and p81 added about +b input 61 ? electrical characteristics 2. recommended operation conditions modified the minimum value of analog reference voltage added s moothing capacitor added the note about less than the minimum power supply voltage 62, 63 ? electrical characteristics 3. dc characteristics (1) current rating changed the table format added main timer mode current added flash memory current move d a/d converter current 65 ? electrical characteristics 4. ac characteristics (1) main clock input characteristics added master clock at ingernal operating clock frequency 66 ? electrical characteristics 4. ac characteristics (3) built - in cr oscillation ch aracteristics added frequency stability time at built - in high - speed cr 67 ? electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main and usb pll (4 - 2) operating conditions of main pll added main pll clock frequency added usb clock frequency added the figure of main pll connection and usb pll connection 68 ? electrical characteristics 4. ac characteristics (6) power - on reset timing added time until releasing power - on reset changed the figure of timing 74 - 81 ? electrical c haracteristics 4. ac characteristics (7) csio/uart timing modified from uart timing to c sio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode d a t a s h e e t 108 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential page section change results 88 ? electrical characteristi cs 5. 12 bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage added conversion time at avcc < 4.5v modified stage transition time to operation permissi on modified the minimum value of reference voltage 91 ? electrical characteristics 6. usb characteristics modified condition of output low level voltage 96 ? electrical characteristics 8. flash memory write/erase characteristics change to the erase time of include write time prior to internal erase 97 - 100 ? el ectrical characteristics 9. return time from low - power consumption mode added return time from low - power consumption mode 103 ? ordering information change to full part number 104 ? package dimensions deleted fpt - 100p - m20 and fpt - 120p - m21 d a t a s h e e t december 15 , 2014 , mb9b500b - ds706 - 00021 - 3v0 - e 109 confidential d a t a s h e e t 110 mb9b500b - ds706 - 00021 - 3v0 - e, december 15 , 2014 confidential coloph on the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injur y, severe physical damage or ot her loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intoler able (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above - mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may co ntain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non - infringement of third - party rights, or any other warranty, express, implied, or statutory. spansion assumes no liability for any damages of any kind arising ou t of the use of the information in this document. copyright ? 2011 - 201 4 spansion all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse tm , ornand tm , easy designsim tm , traveo tm and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. other names used are for informational purposes only and may be trademarks of their respective owners. |
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